# RISC-V Ratified Specifications Library


- [RISC-V Ratified Specifications Library](https://docs.riscv.org/reference//home/index.html)
- [Hardware](https://docs.riscv.org/reference//hardware-overview/index.html)
- [Profiles](https://docs.riscv.org/reference//profiles-overview/index.html)
- [Platform Software](https://docs.riscv.org/reference//platform-software-overview/index.html)
- [Application Enablement](https://docs.riscv.org/reference//app-enablement-overview/index.html)
- [Debug, Trace, and RAS](https://docs.riscv.org/reference//trace-debug-ras-overview/index.html)
- [Platforms](https://docs.riscv.org/reference//platforms-overview/index.html)
- [Specifications Under Development](https://docs.riscv.org/reference//under-dev-overview/index.html)
- [RISC-V Instruction Set Architecture (ISA) Manuals](https://docs.riscv.org/reference//isa/v20260120/index.html)
- [Preamble](https://docs.riscv.org/reference//isa/v20260120/priv/priv-contributors.html)
- [The RISC-V Instruction Set Manual, Volume II](https://docs.riscv.org/reference//isa/v20260120/priv/priv-index.html)
- [Preamble](https://docs.riscv.org/reference//isa/v20260120/unpriv/unpriv-contributors.html)
- [The RISC-V Instruction Set Manual, Volume I](https://docs.riscv.org/reference//isa/v20260120/unpriv/unpriv-index.html)
- [Bibliography](https://docs.riscv.org/reference//isa/v20260120/biblio/bibliography.html)
- [15.1. "H" Extension for Hypervisor Support, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/hypervisor.html)
- [5.1. "Smcsrind/Sscsrind" Indirect CSR Access, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/indirect-csr.html)
- [3.1. Machine-Level ISA, Version 1.13](https://docs.riscv.org/reference//isa/v20260120/priv/machine.html)
- [16.1. Control-flow Integrity (CFI)](https://docs.riscv.org/reference//isa/v20260120/priv/priv-cfi.html)
- [2.1. Control and Status Registers (CSRs)](https://docs.riscv.org/reference//isa/v20260120/priv/priv-csrs.html)
- [20.1. History](https://docs.riscv.org/reference//isa/v20260120/priv/priv-history.html)
- [19.1. RISC-V Privileged Instruction Set Listings](https://docs.riscv.org/reference//isa/v20260120/priv/priv-insns.html)
- [1.1. Introduction](https://docs.riscv.org/reference//isa/v20260120/priv/priv-intro.html)
- [Preface](https://docs.riscv.org/reference//isa/v20260120/priv/priv-preface.html)
- [Historical Rationale for Extensions](https://docs.riscv.org/reference//isa/v20260120/priv/priv-rationale.html)
- [8.1. "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/rnmi.html)
- [9.1. "Smcdeleg/Ssccfg" Counter Delegation Extensions, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smcdeleg.html)
- [7.1. "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smcntrpmf.html)
- [11.1. "Smctr" Control Transfer Records Extension, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smctr.html)
- [10.1. "Smdbltrp" Double Trap Extension, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smdbltrp.html)
- [6.1. "Smepmp" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smepmp.html)
- [4.1. "Smstateen/Ssstateen" Extensions, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/smstateen.html)
- [14.1. "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/sscofpmf.html)
- [17.1. "Ssdbltrp" Double Trap Extension, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/ssdbltrp.html)
- [13.1. "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/priv/sstc.html)
- [12.1. Supervisor-Level ISA, Version 1.13](https://docs.riscv.org/reference//isa/v20260120/priv/supervisor.html)
- [18.1. Pointer Masking Extensions, Version 1.0.0](https://docs.riscv.org/reference//isa/v20260120/priv/zpm.html)
- [13.1. "A" Extension for Atomic Instructions, Version 2.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/a-st-ext.html)
- [30.1. Bit Manipulation Extensions](https://docs.riscv.org/reference//isa/v20260120/unpriv/b-st-ext.html)
- [25.1. "BF16" Extensions for BFloat16-precision Floating-Point, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/bfloat16.html)
- [Bit Manipulation Extensions Assembly Code Examples](https://docs.riscv.org/reference//isa/v20260120/unpriv/bitmanip-examples.html)
- [28.1. "C" Extension for Compressed Instructions, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/c-st-ext.html)
- [Calling Convention for Vector State (Not authoritative - Placeholder Only)](https://docs.riscv.org/reference//isa/v20260120/unpriv/calling-convention.html)
- [20.1. "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/cmo.html)
- [Preface](https://docs.riscv.org/reference//isa/v20260120/unpriv/colophon.html)
- [7.1. "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/counters.html)
- [22.1. "D" Extension for Double-Precision Floating-Point, Version 2.2](https://docs.riscv.org/reference//isa/v20260120/unpriv/d-st-ext.html)
- [21.1. "F" Extension for Single-Precision Floating-Point, Version 2.2](https://docs.riscv.org/reference//isa/v20260120/unpriv/f-st-ext.html)
- [1.1. Introduction](https://docs.riscv.org/reference//isa/v20260120/unpriv/intro.html)
- [12.1. "M" Extension for Integer Multiplication and Division, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/m-st-ext.html)
- [RVWMO Explanatory Material, Version 0.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/mm-eplan.html)
- [Formal Memory Model Specifications, Version 0.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/mm-formal.html)
- [37.1. ISA Extension Naming Conventions](https://docs.riscv.org/reference//isa/v20260120/unpriv/naming.html)
- [23.1. "Q" Extension for Quad-Precision Floating-Point, Version 2.2](https://docs.riscv.org/reference//isa/v20260120/unpriv/q-st-ext.html)
- [Historical Rationale for Extensions](https://docs.riscv.org/reference//isa/v20260120/unpriv/rationale.html)
- [36.1. RV32/64G Instruction Set Listings](https://docs.riscv.org/reference//isa/v20260120/unpriv/rv-32-64g.html)
- [2.1. RV32I Base Integer Instruction Set, Version 2.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/rv32.html)
- [3.1. RV32E and RV64E Base Integer Instruction Sets, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/rv32e.html)
- [4.1. RV64I Base Integer Instruction Set, Version 2.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/rv64.html)
- [18.1. RVWMO Memory Consistency Model, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/rvwmo.html)
- [32.1. Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1](https://docs.riscv.org/reference//isa/v20260120/unpriv/scalar-crypto.html)
- [34.1. Control-flow Integrity (CFI)](https://docs.riscv.org/reference//isa/v20260120/unpriv/unpriv-cfi.html)
- [31.1. "V" Standard Extension for Vector Operations, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/v-st-ext.html)
- [33.1. Cryptography Extensions: Vector Instructions, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/vector-crypto.html)
- [Vector Assembly Code Examples](https://docs.riscv.org/reference//isa/v20260120/unpriv/vector-examples.html)
- [16.1. "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zabha.html)
- [15.1. "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zacas.html)
- [17.1. "Zalasr" Atomic Load-Acquire and Store-Release Instructions, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zalasr.html)
- [14.1. "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01](https://docs.riscv.org/reference//isa/v20260120/unpriv/zawrs.html)
- [29.1. "Zc*" Extension for Code Size Reduction, Version 1.0.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zc.html)
- [26.1. "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zfa.html)
- [24.1. "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zfh.html)
- [27.1. "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zfinx.html)
- [11.1. "Zicond" Extension for Integer Conditional Operations, Version 1.0.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zicond.html)
- [6.1. "Zicsr" Extension for Control and Status Register (CSR) Instructions, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zicsr.html)
- [5.1. "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zifencei.html)
- [8.1. "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zihintntl.html)
- [9.1. "Zihintpause" Extension for Pause Hint, Version 2.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zihintpause.html)
- [35.1. "Zilsd", "Zclsd" Extensions for Load/Store pair for RV32, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zilsd.html)
- [10.1. "Zimop" Extension for May-Be-Operations, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/zimop.html)
- [19.1. "Ztso" Extension for Total Store Ordering, Version 1.0](https://docs.riscv.org/reference//isa/v20260120/unpriv/ztso-st-ext.html)
- [1.1. Changes since Public Review version 0.8](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/changelog.html)
- [4.1. Components of a Profile](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/components.html)
- [Copyright and license information](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/copyright.html)
- [New ISA Extensions](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/extensions.html)
- [Glossary of ISA Extensions](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/glossary.html)
- [RISC-V Profiles](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/index.html)
- [2.1. Introduction.](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/intro.html)
- [3.1. Profiles versus Platforms](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/profilevsplat.html)
- [6.1. RVA20 Profiles](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/rva20.html)
- [7.1. RVA22 Profiles](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/rva22.html)
- [5.1. RVI20 Profiles](https://docs.riscv.org/reference//rva20-rvi20-rva22/v1.0/rvi20.html)
- [1.1. Copyright and license information](https://docs.riscv.org/reference//rva23/v1.0/copyright.html)
- [Glossary of ISA Extensions](https://docs.riscv.org/reference//rva23/v1.0/glossary-of-isa-extensions.html)
- [RVA23 Profile](https://docs.riscv.org/reference//rva23/v1.0/index.html)
- [3.1. Profile-Defined Extensions](https://docs.riscv.org/reference//rva23/v1.0/rv-profile-defined-extensions.html)
- [2.1. RVA Profiles Rationale](https://docs.riscv.org/reference//rva23/v1.0/rva-profile-overview-body.html)
- [4.1. RVA23 Profiles](https://docs.riscv.org/reference//rva23/v1.0/rva23-profiles.html)
- [1.1. Copyright and license information](https://docs.riscv.org/reference//rvb23/v1.0/copyright.html)
- [Glossary of ISA Extensions](https://docs.riscv.org/reference//rvb23/v1.0/glossary.html)
- [RVB23 Profiles](https://docs.riscv.org/reference//rvb23/v1.0/index.html)
- [2.1. Introduction](https://docs.riscv.org/reference//rvb23/v1.0/intro.html)
- [3.1. Profile-Defined Extensions](https://docs.riscv.org/reference//rvb23/v1.0/profile-defined.html)
- [4.1. RVB23 Profiles](https://docs.riscv.org/reference//rvb23/v1.0/rvb23.html)
- [Contributors](https://docs.riscv.org/reference//aia/v1.0/contributors.html)
- [Copyright and license information](https://docs.riscv.org/reference//aia/v1.0/copyright.html)
- [The RISC-V Advanced Interrupt Architecture](https://docs.riscv.org/reference//aia/v1.0/index.html)
- [4.1. Advanced Platform-Level Interrupt Controller (APLIC)](https://docs.riscv.org/reference//aia/v1.0/AdvPLIC.html)
- [2.1. Control and Status Registers (CSRs) Added to Harts](https://docs.riscv.org/reference//aia/v1.0/CSRs.html)
- [3.1. Incoming MSI Controller (IMSIC)](https://docs.riscv.org/reference//aia/v1.0/IMSIC.html)
- [8.1. IOMMU Support for MSIs to Virtual Machines](https://docs.riscv.org/reference//aia/v1.0/IOMMU.html)
- [7.1. Interprocessor Interrupts (IPIs)](https://docs.riscv.org/reference//aia/v1.0/IPIs.html)
- [5.1. Interrupts for Machine and Supervisor Levels](https://docs.riscv.org/reference//aia/v1.0/MSLevel.html)
- [6.1. Interrupts for Virtual Machines (VS Level)](https://docs.riscv.org/reference//aia/v1.0/VSLevel.html)
- [Preface](https://docs.riscv.org/reference//aia/v1.0/colophon.html)
- [1.1. Introduction](https://docs.riscv.org/reference//aia/v1.0/intro.html)
- [Bibliography](https://docs.riscv.org/reference//iommu/v20260222/bibliography.html)
- [Contributors](https://docs.riscv.org/reference//iommu/v20260222/contributors.html)
- [Copyright and license information](https://docs.riscv.org/reference//iommu/v20260222/copyright.html)
- [RISC-V IOMMU Architecture Specification](https://docs.riscv.org/reference//iommu/v20260222/index.html)
- [Data Structures](https://docs.riscv.org/reference//iommu/v20260222/iommu_data_structures.html)
- [Debug support](https://docs.riscv.org/reference//iommu/v20260222/iommu_debug.html)
- [IOMMU Extensions](https://docs.riscv.org/reference//iommu/v20260222/iommu_extensions.html)
- [Hardware guidelines](https://docs.riscv.org/reference//iommu/v20260222/iommu_hw_guidelines.html)
- [In-memory queue interface](https://docs.riscv.org/reference//iommu/v20260222/iommu_in_memory_queues.html)
- [Introduction](https://docs.riscv.org/reference//iommu/v20260222/iommu_intro.html)
- [Preface](https://docs.riscv.org/reference//iommu/v20260222/iommu_preface.html)
- [Memory-mapped register interface](https://docs.riscv.org/reference//iommu/v20260222/iommu_registers.html)
- [Software guidelines](https://docs.riscv.org/reference//iommu/v20260222/iommu_sw_guidelines.html)
- [RISC-V Platform-Level Interrupt Controller Specification](https://docs.riscv.org/reference//plic/v1.0.0/index.html)
- [Change Log](https://docs.riscv.org/reference//plic/v1.0.0/changelog.html)
- [Contributors](https://docs.riscv.org/reference//plic/v1.0.0/contributor.html)
- [1.1. Introduction](https://docs.riscv.org/reference//plic/v1.0.0/introduction.html)
- [Copyright and license information](https://docs.riscv.org/reference//plic/v1.0.0/licensing.html)
- [8.1. Interrupt Claim Process](https://docs.riscv.org/reference//plic/v1.0.0/plic-claims.html)
- [Interrupt Completion](https://docs.riscv.org/reference//plic/v1.0.0/plic-completion.html)
- [6.1. Interrupt Enables](https://docs.riscv.org/reference//plic/v1.0.0/plic-enables.html)
- [5.1. Interrupt Pending Bits](https://docs.riscv.org/reference//plic/v1.0.0/plic-interrupts.html)
- [3.1. Memory Map](https://docs.riscv.org/reference//plic/v1.0.0/plic-memory-map.html)
- [2.1. RISC-V PLIC Operation Parameters](https://docs.riscv.org/reference//plic/v1.0.0/plic-op-parms.html)
- [4.1. Interrupt Priorities](https://docs.riscv.org/reference//plic/v1.0.0/plic-priority.html)
- [7.1. Priority Thresholds](https://docs.riscv.org/reference//plic/v1.0.0/plic-thresholds.html)
- [RISC-V Server SoC Specification](https://docs.riscv.org/reference//server-soc/v1.0/index.html)
- [Copyright and license information](https://docs.riscv.org/reference//server-soc/v1.0/server_soc_preamble.html)
- [Bibliography](https://docs.riscv.org/reference//server-soc/v1.0/server_soc_bibliography.html)
- [Contributors](https://docs.riscv.org/reference//server-soc/v1.0/server_soc_contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//server-soc/v1.0/server_soc_intro.html)
- [2.1. Server SoC Requirements](https://docs.riscv.org/reference//server-soc/v1.0/server_soc_requirements.html)
- [Efficient Trace for RISC-V](https://docs.riscv.org/reference//e-trace/v2.0/index.html)
- [Copyright and license information](https://docs.riscv.org/reference//e-trace/v2.0/preamble.html)
- [Preface](https://docs.riscv.org/reference//e-trace/v2.0/preface.html)
- [3.1. Branch Trace](https://docs.riscv.org/reference//e-trace/v2.0/branchTrace.html)
- [2.1. Encoder Control](https://docs.riscv.org/reference//e-trace/v2.0/control.html)
- [8.1. Data Trace Encoder Output Packets](https://docs.riscv.org/reference//e-trace/v2.0/dataTracePayload.html)
- [11.1. Decoder](https://docs.riscv.org/reference//e-trace/v2.0/decoder.html)
- [10.1. Parameters and Discovery](https://docs.riscv.org/reference//e-trace/v2.0/discovery.html)
- [9.1. Reference Compressed Branch Trace Algorithm](https://docs.riscv.org/reference//e-trace/v2.0/exampleAlgorithm.html)
- [12.1. Example code and packets](https://docs.riscv.org/reference//e-trace/v2.0/exampleCodeSnippets.html)
- [5.1. Filtering](https://docs.riscv.org/reference//e-trace/v2.0/filtering.html)
- [13.1. Code fragment and transport](https://docs.riscv.org/reference//e-trace/v2.0/fragmentCodeAndTransport.html)
- [14.1. Future Directions](https://docs.riscv.org/reference//e-trace/v2.0/future.html)
- [4.1. Hart to encoder interface](https://docs.riscv.org/reference//e-trace/v2.0/ingressPort.html)
- [1.1. Introduction](https://docs.riscv.org/reference//e-trace/v2.0/introduction.html)
- [7.1. Instruction Trace Encoder Output Packets](https://docs.riscv.org/reference//e-trace/v2.0/payload.html)
- [6.1. Timestamping](https://docs.riscv.org/reference//e-trace/v2.0/timestamping.html)
- [RISC-V Capacity and Bandwidth QoS Register Interface](https://docs.riscv.org/reference//cbqri/v1.0/index.html)
- [Copyright and license information](https://docs.riscv.org/reference//cbqri/v1.0/qos_preamble.html)
- [4.1. Bandwidth-controller QoS Register Interface](https://docs.riscv.org/reference//cbqri/v1.0/qos_bandwidth.html)
- [Bibliography](https://docs.riscv.org/reference//cbqri/v1.0/qos_biblio.html)
- [3.1. Capacity-controller QoS Register Interface](https://docs.riscv.org/reference//cbqri/v1.0/qos_capacity.html)
- [Contributors](https://docs.riscv.org/reference//cbqri/v1.0/qos_contributors.html)
- [6.1. Hardware Guidelines](https://docs.riscv.org/reference//cbqri/v1.0/qos_hw_guidelines.html)
- [2.1. QoS Identifiers](https://docs.riscv.org/reference//cbqri/v1.0/qos_identifiers.html)
- [1.1. Introduction](https://docs.riscv.org/reference//cbqri/v1.0/qos_intro.html)
- [5.1. IOMMU Extension for QoS ID](https://docs.riscv.org/reference//cbqri/v1.0/qos_iommu.html)
- [7.1. Software Guidelines](https://docs.riscv.org/reference//cbqri/v1.0/qos_sw_guidelines.html)
- [RISC-V RERI Architecture Specification](https://docs.riscv.org/reference//ras-eri/v1.0/index.html)
- [Copyright and license information](https://docs.riscv.org/reference//ras-eri/v1.0/reri_copyright.html)
- [3.1. Bibliography](https://docs.riscv.org/reference//ras-eri/v1.0/reri_bibliography.html)
- [Contributors](https://docs.riscv.org/reference//ras-eri/v1.0/reri_contributors.html)
- [2.1. Error Reporting](https://docs.riscv.org/reference//ras-eri/v1.0/reri_err_reporting.html)
- [1.1. Introduction](https://docs.riscv.org/reference//ras-eri/v1.0/reri_intro.html)
- [RISC-V Debug Specification](https://docs.riscv.org/reference//debug/v1.0/index.html)
- [4.1. Sdext (ISA Extension)](https://docs.riscv.org/reference//debug/v1.0/Sdext.html)
- [5.1. Sdtrig (ISA Extension)](https://docs.riscv.org/reference//debug/v1.0/Sdtrig.html)
- [3.1. Debug Module (DM) (non-ISA extension)](https://docs.riscv.org/reference//debug/v1.0/debug_module.html)
- [6.1. Debug Transport Module (DTM) (non-ISA extension)](https://docs.riscv.org/reference//debug/v1.0/dtm.html)
- [Hardware Implementations](https://docs.riscv.org/reference//debug/v1.0/implementations.html)
- [1.1. Introduction](https://docs.riscv.org/reference//debug/v1.0/introduction.html)
- [2.1. System Overview](https://docs.riscv.org/reference//debug/v1.0/overview.html)
- [Change Log](https://docs.riscv.org/reference//trace-encap/v1.0/changelog.html)
- [Copyright and license information](https://docs.riscv.org/reference//trace-encap/v1.0/copyright.html)
- [1.1. Contributors](https://docs.riscv.org/reference//trace-encap/v1.0/contributors.html)
- [Packet Encapsulation for E-Trace](https://docs.riscv.org/reference//trace-encap/v1.0/e-trace-specifics.html)
- [3.1. Packet Encapsulation](https://docs.riscv.org/reference//trace-encap/v1.0/encapsulation.html)
- [Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V](https://docs.riscv.org/reference//trace-encap/v1.0/index.html)
- [2.1. Introduction](https://docs.riscv.org/reference//trace-encap/v1.0/intro.html)
- [RISC-V N-Trace (Nexus-based Trace) Specification](https://docs.riscv.org/reference//nexus-trace/v1.0/index.html)
- [13.1. Additional Material](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_additional.html)
- [Change Log](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_changelog.html)
- [Contributors](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_contributors.html)
- [4.1. N-Trace Specific Trace Controls](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_controls.html)
- [Copyright and license information](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_copyright.html)
- [11.1. N-Trace Decoding Guidelines](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_decoding.html)
- [8.1. Field Encoding and Calculation Techniques](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_field_encoding.html)
- [10.1. Rules of Generating Messages](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_generation_rules.html)
- [2.1. Trace Ingress Port](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_ingress_port.html)
- [1.1. Introduction to N-Trace](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_introduction.html)
- [7.1. N-Trace Messages (Details)](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_messages_details.html)
- [6.1. N-Trace Messages (Overview)](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_messages_overview.html)
- [5.1. Main N-Trace Trace Modes](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_modes.html)
- [12.1. IEEE-5001 Nexus Standard Compliance](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_nexus_compliance.html)
- [9.1. Optimization Extensions](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_optimizations.html)
- [3.1. N-Trace Transmission Protocol](https://docs.riscv.org/reference//nexus-trace/v1.0/ntrace_transmission.html)
- [RISC-V Trace Connectors Specification](https://docs.riscv.org/reference//trace-connectors/v1.0/index.html)
- [4.1. Adapters, multiple connectors and on-board debug considerations](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_adapters.html)
- [Change Log](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_changelog.html)
- [Contributors](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_contributors.html)
- [Copyright and license information](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_copyright.html)
- [1.1. Debug and Trace Connectors](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_debug_trace.html)
- [3.1. Mictor 38-bit Debug and Trace Connector](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_mictor38.html)
- [2.1. MIPI20 Debug and Trace Connector](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_mipi20.html)
- [5.1. Rationale (looking at Nexus standard)](https://docs.riscv.org/reference//trace-connectors/v1.0/connectors_rationale.html)
- [RISC-V Trace Control Interface Specification](https://docs.riscv.org/reference//trace-control-interface/v1.0/index.html)
- [Additional Material](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_additional.html)
- [Trace ATB Bridge](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_atb_bridge.html)
- [Change Log](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_changelog.html)
- [Contributors](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_contributors.html)
- [Trace Control Interface Overview](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_control_interface.html)
- [Copyright and license information](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_copyright.html)
- [Trace Encoder Control Interface](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_encoder_control.html)
- [Trace Funnel](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_funnel.html)
- [Introduction](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_introduction.html)
- [Trace PIB Sink](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_pib_sink.html)
- [Trace Protocols and Trace Control](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_protocols.html)
- [Trace RAM Sink](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_ram_sink.html)
- [Trace System Overview](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_system_overview.html)
- [Versioning of Components](https://docs.riscv.org/reference//trace-control-interface/v1.0/tci_versioning.html)
- [Copyright and license information](https://docs.riscv.org/reference//semihosting/v1.0/copyright.html)
- [RISC-V Semihosting](https://docs.riscv.org/reference//semihosting/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//semihosting/v1.0/bibliography.html)
- [2.1. RISC-V Semihosting Binary Interface](https://docs.riscv.org/reference//semihosting/v1.0/binary-interface.html)
- [Contributors](https://docs.riscv.org/reference//semihosting/v1.0/contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//semihosting/v1.0/intro.html)
- [Copyright and license information](https://docs.riscv.org/reference//brs/v1.0/copyright.html)
- [RISC-V Boot and Runtime Services Specification (BRS)](https://docs.riscv.org/reference//brs/v1.0/index.html)
- [6.1. BRS-I ACPI Requirements](https://docs.riscv.org/reference//brs/v1.0/acpi.html)
- [Bibliography](https://docs.riscv.org/reference//brs/v1.0/bibliography.html)
- [Contributors](https://docs.riscv.org/reference//brs/v1.0/contributors.html)
- [3.1. Hart Requirements](https://docs.riscv.org/reference//brs/v1.0/hart.html)
- [1.1. Introduction](https://docs.riscv.org/reference//brs/v1.0/intro.html)
- [2.1. Recipes](https://docs.riscv.org/reference//brs/v1.0/recipes.html)
- [4.1. SBI Requirements](https://docs.riscv.org/reference//brs/v1.0/sbi.html)
- [7.1. BRS-I SMBIOS Requirements](https://docs.riscv.org/reference//brs/v1.0/smbios.html)
- [5.1. BRS-I UEFI Requirements](https://docs.riscv.org/reference//brs/v1.0/uefi.html)
- [Copyright and license information](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/copyright.html)
- [RISC-V Functional Fixed Hardware Specification](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/index.html)
- [Contributors](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/contributors.html)
- [Change Log](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_changelog.html)
- [_CPC Object Examples](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_cpc_examples.html)
- [1.1. Introduction](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_introduction.html)
- [_LPI Object Examples](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_lpi_examples.html)
- [2.1. RISC-V FFH Resource Descriptor Encoding](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_resource_descriptor.html)
- [3.1. Use Cases](https://docs.riscv.org/reference//acpi-ffh/v1.0.1/ffh_use_cases.html)
- [Copyright and license information](https://docs.riscv.org/reference//acpi-rimt/v1.0/copyright.html)
- [RISC-V IO Mapping Table (RIMT)](https://docs.riscv.org/reference//acpi-rimt/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//acpi-rimt/v1.0/bibliography.html)
- [Changelog](https://docs.riscv.org/reference//acpi-rimt/v1.0/changelog.html)
- [Contributors](https://docs.riscv.org/reference//acpi-rimt/v1.0/contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//acpi-rimt/v1.0/intro.html)
- [3.1. ID Mapping Examples](https://docs.riscv.org/reference//acpi-rimt/v1.0/mapping-example.html)
- [2.1. RISC-V IO Mapping Table (RIMT)](https://docs.riscv.org/reference//acpi-rimt/v1.0/rimt-main.html)
- [Terms and Abbreviations](https://docs.riscv.org/reference//acpi-rimt/v1.0/terms.html)
- [Copyright and license information](https://docs.riscv.org/reference//rpmi/v1.0/copyright.html)
- [RISC-V Platform Management Interface Specification (RPMI)](https://docs.riscv.org/reference//rpmi/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//rpmi/v1.0/bibliography.html)
- [Changelog](https://docs.riscv.org/reference//rpmi/v1.0/changelog.html)
- [Contributors](https://docs.riscv.org/reference//rpmi/v1.0/contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//rpmi/v1.0/intro.html)
- [3.1. Messaging Protocol](https://docs.riscv.org/reference//rpmi/v1.0/message-protocol.html)
- [5.1. Integration with SBI MPXY Extension](https://docs.riscv.org/reference//rpmi/v1.0/rpmi-mpxy.html)
- [4.1. Service Groups](https://docs.riscv.org/reference//rpmi/v1.0/service-groups.html)
- [Terms and Abbreviations](https://docs.riscv.org/reference//rpmi/v1.0/terms.html)
- [2.1. Transport](https://docs.riscv.org/reference//rpmi/v1.0/transport.html)
- [Copyright and license information](https://docs.riscv.org/reference//sbi/v3.0/copyright.html)
- [RISC-V Supervisor Binary Interface Specification](https://docs.riscv.org/reference//sbi/v3.0/index.html)
- [3.1. Binary Encoding](https://docs.riscv.org/reference//sbi/v3.0/binary-encoding.html)
- [Change Log](https://docs.riscv.org/reference//sbi/v3.0/changelog.html)
- [Contributors](https://docs.riscv.org/reference//sbi/v3.0/contributors.html)
- [4.1. Base Extension (EID #0x10)](https://docs.riscv.org/reference//sbi/v3.0/ext-base.html)
- [14.1. CPPC Extension (EID #0x43505043 "CPPC")](https://docs.riscv.org/reference//sbi/v3.0/ext-cppc.html)
- [12.1. Debug Console Extension (EID #0x4442434E "DBCN")](https://docs.riscv.org/reference//sbi/v3.0/ext-debug-console.html)
- [19.1. Debug Triggers Extension (EID #0x44425452 "DBTR")](https://docs.riscv.org/reference//sbi/v3.0/ext-debug-triggers.html)
- [21.1. Experimental SBI Extension Space (EIDs #0x08000000 - #0x08FFFFFF)](https://docs.riscv.org/reference//sbi/v3.0/ext-experimental.html)
- [18.1. SBI Firmware Features Extension (EID #0x46574654 "FWFT")](https://docs.riscv.org/reference//sbi/v3.0/ext-firmware-features.html)
- [Firmware Specific Extension Space (EIDs #0x0A000000 - #0x0AFFFFFF)](https://docs.riscv.org/reference//sbi/v3.0/ext-firmware.html)
- [9.1. Hart State Management Extension (EID #0x48534D "HSM")](https://docs.riscv.org/reference//sbi/v3.0/ext-hsm.html)
- [7.1. IPI Extension (EID #0x735049 "sPI: s-mode IPI")](https://docs.riscv.org/reference//sbi/v3.0/ext-ipi.html)
- [5.1. Legacy Extensions (EIDs #0x00 - #0x0F)](https://docs.riscv.org/reference//sbi/v3.0/ext-legacy.html)
- [20.1. Message Proxy Extension (EID #0x4D505859 “MPXY”)](https://docs.riscv.org/reference//sbi/v3.0/ext-mpxy.html)
- [15.1. Nested Acceleration Extension (EID #0x4E41434C "NACL")](https://docs.riscv.org/reference//sbi/v3.0/ext-nested-acceleration.html)
- [11.1. Performance Monitoring Unit Extension (EID #0x504D55 "PMU")](https://docs.riscv.org/reference//sbi/v3.0/ext-pmu.html)
- [8.1. RFENCE Extension (EID #0x52464E43 "RFNC")](https://docs.riscv.org/reference//sbi/v3.0/ext-rfence.html)
- [17.1. Supervisor Software Events Extension (EID #0x535345 "SSE")](https://docs.riscv.org/reference//sbi/v3.0/ext-sse.html)
- [16.1. Steal-time Accounting Extension (EID #0x535441 "STA")](https://docs.riscv.org/reference//sbi/v3.0/ext-steal-time.html)
- [10.1. System Reset Extension (EID #0x53525354 "SRST")](https://docs.riscv.org/reference//sbi/v3.0/ext-sys-reset.html)
- [13.1. System Suspend Extension (EID #0x53555350 "SUSP")](https://docs.riscv.org/reference//sbi/v3.0/ext-sys-suspend.html)
- [6.1. Timer Extension (EID #0x54494D45 "TIME")](https://docs.riscv.org/reference//sbi/v3.0/ext-time.html)
- [22.1. Vendor Specific Extension Space (EIDs #0x09000000 - #0x09FFFFFF)](https://docs.riscv.org/reference//sbi/v3.0/ext-vendor.html)
- [1.1. Introduction](https://docs.riscv.org/reference//sbi/v3.0/intro.html)
- [References](https://docs.riscv.org/reference//sbi/v3.0/references.html)
- [2.1. Terms and Abbreviations](https://docs.riscv.org/reference//sbi/v3.0/terms.html)
- [1.1. Copyright and license information](https://docs.riscv.org/reference//uefi/v1.0.0/copyright.html)
- [RISC-V UEFI PROTOCOL Specification](https://docs.riscv.org/reference//uefi/v1.0.0/index.html)
- [References](https://docs.riscv.org/reference//uefi/v1.0.0/bibliography.html)
- [RISCV_EFI_BOOT_PROTOCOL](https://docs.riscv.org/reference//uefi/v1.0.0/boot_protocol.html)
- [2.1. Contributors](https://docs.riscv.org/reference//uefi/v1.0.0/contributors.html)
- [3.1. Introduction](https://docs.riscv.org/reference//uefi/v1.0.0/intro.html)
- [Copyright and license information](https://docs.riscv.org/reference//rqsc/v1.0/copyright.html)
- [RISC-V Quality of Service Controllers Table (RQSC) ACPI Specification](https://docs.riscv.org/reference//rqsc/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//rqsc/v1.0/bibliography.html)
- [2.1. The ACPI RQSC Table](https://docs.riscv.org/reference//rqsc/v1.0/chapter2.html)
- [3.1. Example ACPI Table Implementation](https://docs.riscv.org/reference//rqsc/v1.0/chapter3.html)
- [Contributors](https://docs.riscv.org/reference//rqsc/v1.0/contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//rqsc/v1.0/intro.html)
- [RISC-V ABIs Specification](https://docs.riscv.org/reference//abi/v1.0/index.html)
- [Status of ABI](https://docs.riscv.org/reference//abi/v1.0/status.html)
- [Terms and Abbreviations](https://docs.riscv.org/reference//abi/v1.0/terms.html)
- [References](https://docs.riscv.org/reference//abi/v1.0/dwarf-bib.html)
- [References](https://docs.riscv.org/reference//abi/v1.0/elf-bib.html)
- [Introduction](https://docs.riscv.org/reference//abi/v1.0/introduction.html)
- [undefined](https://docs.riscv.org/reference//abi/v1.0/preamble.html)
- [4.1. C/C++ type details](https://docs.riscv.org/reference//abi/v1.0/riscv-cc-c-cpp-type-details.html)
- [Linux-specific ABI](https://docs.riscv.org/reference//abi/v1.0/riscv-cc-linux-specific-abi.html)
- [2.1. Procedure Calling Convention](https://docs.riscv.org/reference//abi/v1.0/riscv-cc-procedure-calling-convention.html)
- [1.1. Register Convention](https://docs.riscv.org/reference//abi/v1.0/riscv-cc-register-convention.html)
- [3.1. Calling Convention for System Calls](https://docs.riscv.org/reference//abi/v1.0/riscv-cc-system-calls.html)
- [10.1. DWARF Debugging Format](https://docs.riscv.org/reference//abi/v1.0/riscv-dwarf-debugging-format.html)
- [11.1. DWARF Register Numbers](https://docs.riscv.org/reference//abi/v1.0/riscv-dwarf-register-numbers.html)
- [5.1. Code models](https://docs.riscv.org/reference//abi/v1.0/riscv-elf-code-models.html)
- [7.1. C++ Name Mangling](https://docs.riscv.org/reference//abi/v1.0/riscv-elf-cpp-name-mangling.html)
- [6.1. Dynamic Linking](https://docs.riscv.org/reference//abi/v1.0/riscv-elf-dynamic-linking.html)
- [9.1. Linker Relaxation](https://docs.riscv.org/reference//abi/v1.0/riscv-elf-linker-relaxation.html)
- [8.1. ELF Object Files](https://docs.riscv.org/reference//abi/v1.0/riscv-elf-object-files.html)
- [Contributors](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/contributors.html)
- [Copyright and license information](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/copyright.html)
- [RISC-V Vector C Intrinsic Specification Document](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/bibliography.html)
- [2.1. Examples](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/rvv-intrinsic-examples.html)
- [1.1. Introduction](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/rvv-intrinsic-spec.html)
- [Vector Loads and Stores Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/00_vector_loads_and_stores_intrinsics.html)
- [Vector Loads and Stores Segment Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/01_vector_loads_and_stores_segment_intrinsics.html)
- [Vector Integer Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/02_vector_integer_arithmetic_intrinsics.html)
- [Vector Fixed-Point Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.html)
- [Vector Floating-Point Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/04_vector_floating-point_intrinsics.html)
- [Vector Reduction Operations](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/05_vector_reduction_operations.html)
- [Vector Mask Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/06_vector_mask_intrinsics.html)
- [Vector Permutation Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/07_vector_permutation_intrinsics.html)
- [Miscellaneous Vector Utility Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/intrinsic_funcs/08_miscellaneous_vector_utility_intrinsics.html)
- [Vector Loads and Stores Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/00_vector_loads_and_stores_intrinsics.html)
- [Vector Loads and Stores Segment Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/01_vector_loads_and_stores_segment_intrinsics.html)
- [Vector Integer Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/02_vector_integer_arithmetic_intrinsics.html)
- [Vector Fixed-Point Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.html)
- [Vector Floating-Point Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/04_vector_floating-point_intrinsics.html)
- [Vector Reduction Operations](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/05_vector_reduction_operations.html)
- [Vector Mask Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/06_vector_mask_intrinsics.html)
- [Miscellaneous Vector Utility Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/08_miscellaneous_vector_utility_intrinsics.html)
- [Vector Permutation Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/overloaded_intrinsic_funcs/07_vector_permutation_intrinsics.html)
- [Vector Loads and Stores Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/00_vector_loads_and_stores_intrinsics.html)
- [Vector Loads and Stores Segment Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/01_vector_loads_and_stores_segment_intrinsics.html)
- [Vector Integer Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/02_vector_integer_arithmetic_intrinsics.html)
- [Vector Floating-Point Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/04_vector_floating-point_intrinsics.html)
- [Vector Fixed-Point Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.html)
- [Vector Reduction Operations](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/05_vector_reduction_operations.html)
- [Vector Mask Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/06_vector_mask_intrinsics.html)
- [Vector Permutation Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/07_vector_permutation_intrinsics.html)
- [Miscellaneous Vector Utility Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/overloaded_intrinsic_funcs/08_miscellaneous_vector_utility_intrinsics.html)
- [Vector Loads and Stores Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/00_vector_loads_and_stores_intrinsics.html)
- [Vector Loads and Stores Segment Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/01_vector_loads_and_stores_segment_intrinsics.html)
- [Vector Integer Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/02_vector_integer_arithmetic_intrinsics.html)
- [Vector Fixed-Point Arithmetic Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.html)
- [Vector Floating-Point Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/04_vector_floating-point_intrinsics.html)
- [Vector Reduction Operations](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/05_vector_reduction_operations.html)
- [Vector Mask Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/06_vector_mask_intrinsics.html)
- [Vector Permutation Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/07_vector_permutation_intrinsics.html)
- [Miscellaneous Vector Utility Intrinsics](https://docs.riscv.org/reference//vector-c-intrinsics/v1.0/policy_funcs/intrinsic_funcs/08_miscellaneous_vector_utility_intrinsics.html)
- [Copyright and license information](https://docs.riscv.org/reference//server-platform/v1.0/copyright.html)
- [The RISC-V Server Platform](https://docs.riscv.org/reference//server-platform/v1.0/index.html)
- [Bibliography](https://docs.riscv.org/reference//server-platform/v1.0/server_platform_bibliography.html)
- [Contributors](https://docs.riscv.org/reference//server-platform/v1.0/server_platform_contributors.html)
- [1.1. Introduction](https://docs.riscv.org/reference//server-platform/v1.0/server_platform_intro.html)
- [2.1. Server Platform Hardware Rules](https://docs.riscv.org/reference//server-platform/v1.0/server_platform_requirements.html)