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  • Advanced Interrupt Architecture
    • Title Page
    • Contributors
    • Preface
    • Copyright
    • Chapter 1. Introduction
    • Chapter 2. CSRs Added to Harts
    • Chapter 3. Incoming MSI Controller (IMSIC)
    • Chapter 4. Advanced PLIC (APLIC)
    • Chapter 5. Interrupts for Machine and Supervisor Levels
    • Chapter 6. Interrupts for Virtual Machines (VS Level)
    • Chapter 7. Interprocessor Interrupts (IPIs)
    • Chapter 8. IOMMU Support for MSIs to Virtual Machines
  • RISC-V IOMMU
    • Title Page
    • Copyright and License Information
    • Contributors
    • Preface
    • Chapter 1. Introduction
    • Chapter 2. Data Structures
    • Chapter 3. In-memory Queue Interface
    • Chapter 4. Debug Support
    • Chapter 5. Memory-mapped Register Interface
    • Chapter 6. Software Guidelines
    • Chapter 7. Hardware Guidelines
    • Chapter 8. IOMMU Extensions
    • Bibliography
  • Platform-Level Interrupt Controller
    • Title Page
    • Changelog
    • Copyright and license
    • Contributors
    • Chapter 1. Introduction
    • Chapter 2. RISC-V PLIC Operation Parameters
    • Chapter 3. Memory Map
    • Chapter 4. Interrupt Priorities
    • Chapter 5. Interrupt Pending Bits
    • Chapter 6. Interrupt Enables
    • Chapter 7. Priority Thresholds
    • Chapter 8. Interrupt Claim Process
    • Chapter 9. Interrupt Completion
  • Server SoC
    • Title Page
    • Copyright and License
    • Contributors
    • Chapter 1. Introduction
    • Chapter 2. Server SoC Requirements
    • Bibliography
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RISCV

The RISC-V Advanced Interrupt Architecture

Editors: John Hauser

Version 1.0, Revised 20250312

This document is in the Ratified state

No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised.
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