RISCV RISCV
Library
ISA
Unprivileged Privileged
Profiles
RVA23 Profile RVB23 Profile RISC-V Profiles
Non-ISA Hardware
Advanced Interrupt Architecture IOMMU Architecture Platform-Level Interrupt Controller Server SOC
Debug, Trace, RAS
Efficient Trace < QoS Register Interface Debug N-Trace RERI Architecture Trace Connectors Trace Control Interface Unformatted Trace and Diagnostic Data Packet Encapsulation
Platform Software
Boot and Runtime Services Functional Fixed Hardware IO Mapping Table Platform Management Interface Semihosting Supervisor Binary Interface UEFI Protocol
App Enablement
Application Binary Interface Vector C Intrinsic
  • RISC-V Specifications
ISA Specifications
  • Volume I: RISC-V Unprivileged ISA Specification
    • Title Page
    • Preamble
    • Preface
    • Chapter 1. Introduction
    • Chapter 2. RV32I Base Integer Instruction Set, Version 2.1
    • Chapter 3. RV32E and RV64E Base Integer Instruction Sets, Version 2.0
    • Chapter 4. RV64I Base Integer Instruction Set, Version 2.1
    • Chapter 5. "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
    • Chapter 6. "Zicsr", Extension for Control and Status Register (CSR) Instructions, Version 2.0
    • Chapter 7. "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
    • Chapter 8. "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0
    • Chapter 9. "Zihintpause" Extension for Pause Hint, Version 2.0
    • Chapter 10. "Zimop" Extension for May-Be-Operations, Version 1.0
    • Chapter 11. "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
    • Chapter 12. "M" Extension for Integer Multiplication and Division, Version 2.0
    • Chapter 13. "A" Extension for Atomic Instructions, Version 2.1
    • Chapter 14. "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
    • Chapter 15. "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0
    • Chapter 16. "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0
    • Chapter 17. "Zalasr" Atomic Load-Acquire and Store-Release Instructions, Version 1.0
    • Chapter 18. RVWMO Memory Consistency Model, Version 2.0
    • Chapter 19. "Ztso" Extension for Total Store Ordering, Version 1.0
    • Chapter 20. "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0
    • Chapter 21. "F" Extension for Single-Precision Floating-Point, Version 2.2
    • Chapter 22. "D" Extension for Double-Precision Floating-Point, Version 2.2
    • Chapter 23. "Q" Extension for Quad-Precision Floating-Point, Version 2.2
    • Chapter 24. "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0
    • Chapter 25. "BF16" Extensions for for BFloat16-precision Floating-Point, Version 1.0
    • Chapter 26. "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0
    • Chapter 27. "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0
    • Chapter 28. "C" Extension for Compressed Instructions, Version 2.0
    • Chapter 29. "Zc*" Extension for Code Size Reduction, Version 1.0.0
    • Chapter 30. "B" Extension for Bit Manipulation, Version 1.0.0
    • Chapter 31. "V" Standard Extension for Vector Operations, Version 1.0
    • Chapter 32. Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
    • Chapter 33. Cryptography Extensions: Vector Instructions, Version 1.0
    • Chapter 34. Control-flow Integrity (CFI)
    • Chapter 35. "Zilsd", "Zclsd" Extensions for Load/Store pair for RV32, Version 1.0
    • Chapter 36. RV32/64G Instruction Set Listings
    • Chapter 37. ISA Extension Naming Conventions
    • Appendix A. RVWMO Explanatory Material, Version 0.1
    • Appendix B. Formal Memory Model Specifications, Version 0.1
    • Appendix C. Vector Assembly Code Examples
    • Appendix D. Calling Convention for Vector State (Not authoritative - Placeholder Only)
    • Appendix E. Bit Manipulation Extensions Assembly Code Examples
    • Appendix F. Historical Rationale for Extensions
  • Volume II: RISC-V Privileged ISA Specification
    • Title Page
    • Preamble
    • Preface
    • Chapter 1. Introduction
    • Chapter 2. Control and Status Registers (CSRs)
    • Chapter 3. Machine-Level ISA, Version 1.13
    • Chapter 4. "Smstateen/Ssstateen" Extensions, Version 1.0
    • Chapter 5. "Smcsrind/Sscsrind" Indirect CSR Access, version 1.0
    • Chapter 6. "Smepmp" Extension for PMP Enhancements, Version 1.0
    • Chapter 7. "Smcntrpmf" Cycke and Instret Privilege Mode Filtering, Version 1.0
    • Chapter 8. "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0
    • Chapter 9. "Smcdeleg" Counter Delegation Extension, Version 1.0
    • Chapter 10. "Smdbltrp" Double Trap Extension, Version 1.0
    • Chapter 11. "Smctr" Control Transfer Records Extension, Version 1.0
    • Chapter 12. Supervisor-Level ISA, Version 1.13
    • Chapter 13. "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0
    • Chapter 14. "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0
    • Chapter 15. "H" Extension for Hypervisor Support, Version 1.0
    • Chapter 16. Control-flow Integrity(CFI)
    • Chapter 17. "Ssdbltrp" Double Trap Extension, Version 1.0
    • Chapter 18. Pointer Masking Extensions, Version 1.0.0
    • Chapter 19. RISC-V Privileged Instruction Set Listings
    • Chapter 20. History
    • Appendix A. Historical Rationale for Extensions
  • Bibliography
    • Bibliography
Report a Problem GitHub Project More Details Download PDF
  • ISA Specifications
  • Volume II: RISC-V Privileged ISA Specification
  • Title Page
RISCV

The RISC-V Instruction Set Manual, Volume II

Privileged Architecture

Version 20260120: Official Release

Appendix F. Historical Rationale for Extensions Preamble
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