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  • RISC-V Specifications
Debug, Trace, RAS
  • Debug Specification
    • Title Page
    • Chapter 1. Introduction
    • Chapter 2. Overview
    • Chapter 3. Debug Module
    • Chapter 4. Sdext (ISA Extension)
    • Chapter 5. Sdtrig (ISA Extension)
    • Chapter 6. Debug Transport Module (DTM)
    • Appendix A. Hardware Implementations
  • Efficient Trace for RISC-V
    • Title Page
    • Copyright and license information
    • Preface
    • Chapter 1. Introduction
    • Chapter 2. Control
    • Chapter 3. Branch Trace
    • Chapter 4. Ingress Port
    • Chapter 5. Filtering
    • Chapter 6. Timestamping
    • Chapter 7. Payload
    • Chapter 8. Data Trace Payload
    • Chapter 9. Example Algorithm
    • Chapter 10. Discovery
    • Chapter 11. Decoder
    • Chapter 12. Example Code Snippets
    • Chapter 13. Fragment Code and Transport
    • Chapter 14. Future
  • N-Trace
    • Title Page
    • Change Log
    • Copyright and License
    • Contributors
    • Chapter 1. Introduction to N-Trace
    • Chapter 2. Trace Ingress Port
    • Chapter 3. Transmission Protocol
    • Chapter 4. Trace Controls
    • Chapter 5. Trace Modes
    • Chapter 6. Messages Overview
    • Chapter 7. Messages Details
    • Chapter 8. Field Encoding
    • Chapter 9. Optimization Extensions
    • Chapter 10. Message Generation Rules
    • Chapter 11. Decoding Guidelines
    • Chapter 12. Nexus Compliance
    • Chapter 13. Additional Material
  • QoS Register Interface
    • Title Page
    • Copyright and license information
    • Contributors
    • Chapter 1. Introduction
    • Chapter 2. QoS Identifiers
    • Chapter 3. Capacity-controller QoS Register Interface
    • Chapter 4. Bandwidth-controller QoS Register Interface
    • Chapter 5. IOMMU Extension for QoS ID
    • Chapter 6. Hardware Guidelines
    • Chapter 7. Software Guidelines
    • Bibliography
  • RERI Architecture
    • Title Page
    • Copyright and License Information
    • Contributors
    • Chapter 1. Introduction
    • Chapter 2. Error Reporting
    • Chapter 3. Bibliography
  • Trace Connectors
    • Title Page
    • Change Log
    • Copyright and License
    • Contributors
    • Chapter 1. Debug and Trace Extensions
    • Chapter 2. MIPI20 Connector
    • Chapter 3. Mictor-38 Connector
    • Chapter 4. Adapters and On-Board Debug
    • Chapter 5. Rationale and Standards
  • Trace Control Interface
    • Title Page
    • Change Log
    • Copyright and License
    • Contributors
    • Chapter 1. Introduction
    • Chapter 2. Trace Protocols and Control
    • Chapter 3. Trace System Overview
    • Chapter 4. Trace Control Interface Overview
    • Chapter 5. Versioning of Components
    • Chapter 6. Trace Encoder Control Interface
    • Chapter 7. Trace RAM Sink
    • Chapter 8. Trace Funnel
    • Chapter 9. Trace PIB Sink
    • Chapter 10. Trace ATB Bridge
    • Chapter 11. Additional Material
  • Unformatted Trace & Data Encapsulation
    • Title Page
    • Change Log
    • Copyright
    • Chapter 1. Contributors
    • Chapter 2. Introduction
    • Chapter 3. Encapsulation Format
    • E-Trace Specifics
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  • RISC-V Specifications
  • Debug, Trace, RAS Overview
  • RERI Architecture
  • Title Page
RISCV

RISC-V RERI Architecture Specification

RERI Task Group

Version v1.0, 2024-05-24: Ratified

This document is in the Ratified state

No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised.
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