ISA Specifications Volume II: RISC-V Privileged ISA Specification "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0 For the latest stable version, please use ISA Specifications Latest! 1. "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0 The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits. If the Svadu extension is implemented, the menvcfg.ADUE field is writable. If the hypervisor extension is additionally implemented, the henvcfg.ADUE field is also writable. See Machine Environment Configuration Register and Hypervisor Environment Configuration Register for the definitions of those fields. Addressing and Memory Protection defines the semantics of hardware updating of A/D bits. When hardware updating of A/D bits is disabled, the Svade extension, which mandates exceptions when A/D bits need be set, instead takes effect. The Svade extension is also defined in Addressing and Memory Protection. "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0