RISC-V Ratified Specifications Library
Welcome to the RISC-V Ratified Specifications Library. This site provides access to all ratified RISC-V specifications.
About RISC-V
RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. These specifications are maintained by RISC-V International and represent the ratified, stable specifications for the RISC-V ecosystem.
For more information, visit riscv.org.
Core Architecture
Unprivileged ISA
User-level instruction set and standard extensions.
Privileged ISA
Privileged architecture, execution modes, and system control.
Profiles
RISC-V Profiles
Base profile definitions and guidance.
RVA23 Profile
Application-class profile requirements.
RVB23 Profile
Embedded and edge profile requirements.
Hardware
Advanced Interrupt Architecture
Interrupt architecture and related interfaces.
IOMMU
IOMMU architecture, registers, queues, and integration guidance.
Platform-Level Interrupt Controller
Interrupt controller behavior and programming model.
Server SoC
Server-class SoC requirements and conventions.
Debug, Trace, and RAS
Efficient Trace for RISC-V
Trace architecture for efficient execution visibility.
QoS Register Interface
QoS register interface for capacity and bandwidth control.
RERI Architecture
Reliability, availability, and serviceability error records.
Debug Specification
Defines the interfaces for external debugging of RISC-V processors.
Unformatted Trace & Data Encapsulation
Encapsulation format for emitted trace data.
N-Trace
Nexus-based trace data formatting and transport.
Trace Connectors
Connector definitions for trace interoperability.
Trace Control Interface
Control and configuration interface for trace features.
Platform Software
Semihosting
Semihosting interface for development and debugging.
Boot and Runtime Services
Boot-time and runtime software interface requirements.
Functional Fixed Hardware
FFH interface definitions for platform integration.
IO Mapping Table
Standardized interrupt mapping table format.
Platform Management Interface
Platform management services and messaging definitions.
Supervisor Binary Interface
Standard interface between supervisor software and firmware.
UEFI PROTOCOL
Defines a software interface between an operating system and platform firmware.
Application Enablement
Application Binary Interface
Application binary interface definitions for ELF tooling.
Vector C Intrinsic
Compiler intrinsics for vector extension programming.