RISCV
Library
ISA
Unprivileged Privileged
Profiles
RVA23 Profile RVB23 Profile RISC-V Profiles
Non-ISA Hardware
Advanced Interrupt Architecture IOMMU Architecture Platform-Level Interrupt Controller Server SOC
Debug, Trace, RAS
Efficient Trace < QoS Register Interface Debug N-Trace RERI Architecture Trace Connectors Trace Control Interface Unformatted Trace and Diagnostic Data Packet Encapsulation
Platform Software
Boot and Runtime Services Functional Fixed Hardware IO Mapping Table Platform Management Interface Semihosting Supervisor Binary Interface UEFI Protocol
App Enablement
Application Binary Interface Vector C Intrinsic
ISA Specifications
  • Volume I: RISC-V Unprivileged ISA Specification
    • Unprivileged Architecture
    • Preamble
    • Preface
    • Chapter 1. Introduction
    • Chapter 2. RV32I Base Integer Instruction Set, Version 2.1
    • Chapter 3. RV32E and RV64E Base Integer Instruction Sets, Version 2.0
    • Chapter 4.RV64I Base Integer Instruction Set, Version 2.1
    • Chapter 5. RV128I Base Integer Instruction Set, Version 1.7
    • Chapter 6. "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
    • Chapter 7."Zicsr", Extension for Control and Status Register (CSR) Instructions, Version 2.0
    • Chapter 8. "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
    • Chapter 9. "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0
    • Chapter 10. "Zihintpause" Extension for Pause Hint, Version 2.0
    • Chapter 11. "Zimop" Extension for May-Be-Operations, Version 1.0
    • Chapter 12. "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
    • Chapter 13. "M" Extension for Integer Multiplication and Division, Version 2.0
    • Chapter 14. "A" Extension for Atomic Instructions, Version 2.1
    • Chapter 15. "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
    • Chapter 16. "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0
    • Chapter 17. RVWMO Memory Consistency Model, Version 2.0
    • Chapter 18. "Ztso" Extension for Total Store Ordering, Version 1.0
    • Chapter 19. "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0
    • Chapter 20. "F" Extension for Single-Precision Floating-Point, Version 2.2
    • Chapter 21. "D" Extension for Double-Precision Floating-Point, Version 2.2
    • Chapter 22. "Q" Extension for Quad-Precision Floating-Point, Version 2.2
    • Chapter 23. "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0
    • Chapter 24. "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0
    • Chapter 25. "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0
    • Chapter 26. "C" Extension for Compressed Instructions, Version 2.0
    • Chapter 27. "Zc*" Extension for Code Size Reduction, Version 1.0.0
    • Chapter 28. "B" Extension for Bit Manipulation, Version 1.0.0
    • Chapter 29. "J" Extension for Dynamically Translated Languages, Version 1.0.0
    • Chapter 30. "P" Extension for Packed SIMD Instructions, Version 1.0.0
    • Chapter 31. "V" Standard Extension for Vector Operations, Version 1.0
    • Chapter 32. Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
    • Chapter 33.Cryptography Extensions: Vector Instructions, Version 1.0
    • Chapter 34. RV32/64G Instruction Set Listings
    • Chapter 35. Appendix: Extending the RISC-V ISA
    • Chapter 36. ISA Extension Naming Conventions
    • Chapter 37. Document Revision History
    • Appendix A: RVWMO Explanatory Material, Version 0.1
    • Appendix B: Formal Memory Model Specifications, Version 0.1
    • Appendix C: Vector Assembly Code Examples
    • Appendix D: Calling Convention for Vector State (Not authoritative - Placeholder Only)
  • Volume II: RISC-V Privileged ISA Specification
    • Privileged Architecture
    • Preamble
    • Preface
    • Introduction
    • Control and Status Registers (CSRs)
    • Machine-Level ISA, Version 1.13
    • "Smstateen/Ssstateen" Extensions, Version 1.0
    • "Smcsrind/Sscsrind" Indirect CSR Access, version 1.0
    • "Smepmp" Extension for PMP Enhancements, Version 1.0
    • "Smcntrpmf" Cycke and Instret Privilege Mode Filtering, Version 1.0
    • "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0
    • "Smcdeleg" Counter Delegation Extension, Version 1.0
    • Supervisor-Level ISA, Version 1.13
    • "Svnapot" Extension for NAPOT Translation Contiguity, Version 1.0
    • "Svpbmt" Extension for Page-Based Memory Types, Version 1.0
    • "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
    • "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0
    • "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0
    • "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0
    • "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0
    • "H" Extension for Hypervisor Support, Version 1.0
    • RISC-V Privileged Instruction Set Listings
    • History
  • Bibliography
    • Bibliography
Report a Problem GitHub Project
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  • Unprivileged ISA
  • Privileged ISA
  • ISA Specifications
  • Volume II: RISC-V Privileged ISA Specification
  • Privileged Architecture

For the latest stable version, please use ISA Specifications Latest!

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Volume II: Privileged Architecture

RISCV

Version 20240411: This document is in Ratified state.

Appendix D: Calling Convention for Vector State (Not authoritative - Placeholder Only) Preamble
  • ISA Specifications
    • Latest
    • Version: 20240411

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