Debug, Trace, and RAS

Trace architecture for efficient execution visibility.

QoS register interface for capacity and bandwidth control.

Reliability, availability, and serviceability error records.

Defines the interfaces for external debugging of RISC-V processors.

Encapsulation format for emitted trace data.

Nexus-based trace data formatting and transport.

Connector definitions for trace interoperability.

Control and configuration interface for trace features.