3.1. Use Cases

3.1.1. Lower Power Idle States

It is desirable for RISC-V system harts to transition to lower power states when they go idle. ACPI provides Lower Power Idle State (_LPI) objects which support an operating system’s implementation of transitioning to lower power states. The following subsections specify some fields of the _LPI object for RISC-V systems. Refer to the ACPI specification for all remaining fields.

3.1.1.1. Entry Method

The _LPI object uses a “Resource Descriptor”, which is formatted per Chapter 2, to specify the entry method for a lower power state. RISC-V systems set the resource descriptor as specified in Table 2:

Table 2. LPI Entry Method
Field Value

Address Space

0x7F (FFixedHW)

Register Bit Width

64

Register Bit Offset

0

Access Size

4 (QWord)

Register Address

As specified in the Bits[63:60], Bits[59:32], and Bits[31:0] columns of Table 3
Table 3. LPI Entry Method Address
Bits[63:60]
(Type)		 Bits[59:32] Bits[31:0] Description

0x0

0x000_0000

0x0000_0000

WFI

0x1

0x000_0000

SBI HSM hart
suspend type

Suspend the hart using
the SBI HSM extension

All other encodings for LPI entry methods with Address Space set to FFixedHW (0x7f) are reserved for future use.

3.1.1.2. Arch. Context Lost Flags

_LPI objects also provide an Arch. Context Lost Flags field, which is a 32-bit integer, and may be used to indicate what processor context is lost. RISC-V _LPI objects must have appropriate flags set in this field as specified in Table 4:

Table 4. LPI Arch. Context Lost Flags
Bit offset Bit width Description

0

1

Set when the hart timer context is lost.

1

31

Reserved. Must be zero.

Appemdix A provides examples for both a WFI entry method and SBI HSM hart suspend entry methods.

3.1.2. Collaborative Processor Performance Control

ACPI describes the Collaborative Processor Performance Control (CPPC) mechanism, which is an abstract and flexible mechanism for the operating system to collaborate with an entity in the platform to manage the performance of the harts. The platform entity may be the hart itself, the platform chipset, or a separate controller.

The ACPI _CPC object provides a way for the operating system to transition the hart into a performance state selected from an abstract, continuous range of values. Fields in the _CPC object may be static integers or “Resource Descriptors”. The following subsection specifies a RISC-V system “Resource Descriptor” for the _CPC object.

3.1.2.1. _CPC Object Resource Descriptor

The _CPC object may use a “Resource Descriptor”, which is formatted per Chapter 2, for many of its fields. When using an FFH Resource Descriptor for a _CPC field, it must be formatted as specified in Table 5:

Table 5. _CPC Resource Descriptor
Field Value

Address Space

0x7F (FFixedHW)

Register Bit Width

64

Register Bit Offset

0

Access Size

4 (QWord)

Register Address

As specified in the Bits[63:60], Bits[59:32], Bits[31:12] and Bits[11:0] columns of Table 6
Table 6. _CPC Register Address
Bits[63:60]
(Type)		 Bits[59:32] Bits[31:12] Bits[11:0] Description

0x1

0x000_0000

SBI CPPC Register ID

SBI CPPC access

0x2

0x000_0000

0x00000

CSR number

CSR access

All other encodings for _CPC Resource Descriptors with Address Space set to FFixedHW (0x7f) are reserved for future use.

Appendix B provides examples for both a CSR access and an SBI CPPC access.