This RISC-V specification has been contributed to directly or indirectly by:

Abner Chang <abner.chang@hpe.com>
Al Stone <ahs3@ahs3.net>
Andrew Jones <ajones@ventanamicro.com>
Anup Patel <apatel@ventanamicro.com>
Atish Patra <atishp04@gmail.com>
Atish Patra <atishp@rivosinc.com>
Bin Meng <bmeng.cn@gmail.com>
Chris Williams <diodesign@tuta.io>
Clément Léger <cleger@rivosinc.com>
Conor Dooley <conor.dooley@microchip.com>
Daniel Schaefer <git@danielschaefer.me>
Esteban Blanc <estblcsk@gmail.com>
hasheddan <georgedanielmangum@gmail.com>
Heinrich Schuchardt <xypron.glpk@gmx.de>
Jeff Scheel <jeff@riscv.org>
Jessica Clarke <jrtc27@jrtc27.com>
john <799433746@qq.com>
Konrad Schwarz <konrad.schwarz@siemens.com>
Luo Jia / Zhouqi Jiang <luojia@hust.edu.cn>
Nick Kossifidis <mickflemm@gmail.com>
Palmer Dabbelt <palmer@dabbelt.com>
Paolo Bonzini <pbonzini@redhat.com>
Rahul Pathak <rpathak@ventanamicro.com>
Samuel Holland <samuel.holland@sifive.com>
Sean Anderson <seanga2@gmail.com>
Stefano Stabellini <stefano.stabellini@amd.com>
Sunil V L <sunilvl@ventanamicro.com>
Tsukasa OI <research_trasio@irq.a4lg.com>
Yiting Wang <yiting.wang@windriver.com>