RISCV RISCV
Home Home
  • RISC-V Specifications
Debug, Trace, and RAS
  • Debug Specification
    • Title Page
    • Chapter 1. Introduction
    • Chapter 2. Overview
    • Chapter 3. Debug Module
    • Chapter 4. Sdext (ISA Extension)
    • Chapter 5. Sdtrig (ISA Extension)
    • Chapter 6. Debug Transport Module (DTM)
    • Appendix A. Hardware Implementations
    • Appendix B. Debugger Implementation
    • Efficient Trace for RISC-V
      • Copyright and license information
      • Preface
      • Introduction
      • Chapter 1. Control
      • Chapter 2. Branch Trace
      • Chapter 3. Ingress Port
      • Chapter 4. Filtering
      • Chapter 5. Timestamping
      • Chapter 6. Payload
      • Chapter 7. Data Trace Payload
      • Chapter 8. Example Algorithm
      • Chapter 9. Discovery
      • Chapter 10. Decoder
      • Chapter 11. Example Code Snippets
      • Chapter 12. Fragment Code and Transport
      • Chapter 13. Future
    • HART Trace Interface
      • Contributors
      • Introduction
      • Chapter 1. HART Trace Interface Specification
      • Chapter 2. Extensions
      • Bibliography
    • N-Trace
      • Change Log
      • Copyright and License
      • Contributors
      • Introduction to N-Trace
      • Chapter 1. Trace Ingress Port
      • Chapter 2. Transmission Protocol
      • Chapter 3. Trace Controls
      • Chapter 4. Trace Modes
      • Chapter 5. Messages Overview
      • Chapter 6. Messages Details
      • Chapter 7. Field Encoding
      • Chapter 8. Optimization Extensions
      • Chapter 9. Message Generation Rules
      • Chapter 10. Decoding Guidelines
      • Chapter 11. Nexus Compliance
      • Chapter 12. Additional Material
    • QoS Register Interface
      • Copyright and license information
      • Contributors
      • Introduction
      • Chapter 1. QoS Identifiers
      • Chapter 2. Capacity-controller QoS Register Interface
      • Chapter 3. Bandwidth-controller QoS Register Interface
      • Chapter 4. IOMMU Extension for QoS ID
      • Chapter 5. Hardware Guidelines
      • Chapter 6. Software Guidelines
      • Chapter 7. Bibliography
    • RERI Architecture
      • Copyright and License Information
      • Contributors
      • Introduction
      • Chapter 1. Error Reporting
      • Chapter 2. Bibliography
    • Trace Connectors
      • Change Log
      • Copyright and License
      • Contributors
      • Debug and Trace Extensions
      • Chapter 1. MIPI20 Connector
      • Chapter 2. Mictor-38 Connector
      • Chapter 3. Adapters and On-Board Debug
      • Chapter 4. Rationale and Standards
    • Trace Control Interface
      • Change Log
      • Copyright and License
      • Contributors
      • Introduction
      • Chapter 1. Trace Protocols and Control
      • Chapter 2. Trace System Overview
      • Chapter 3. Trace Control Interface Overview
      • Chapter 4. Versioning of Components
      • Chapter 5. Trace Encoder Control Interface
      • Chapter 6. Trace RAM Sink
      • Chapter 7. Trace Funnel
      • Chapter 8. Trace PIB Sink
      • Chapter 9. Trace ATB Bridge
      • Chapter 10. Additional Material
    • Unformatted Trace & Data Encapsulation
      • Change Log
      • Copyright
      • Contributors
      • Chapter 1. Introduction
      • Chapter 2. Encapsulation Format
      • Chapter 3. E-Trace Specifics
Report a Problem GitHub Project More Details Download PDF
  • RISC-V Specifications
  • Debug, Trace, RAS Overview
  • HART Trace Interface

Contributors

Contributors

This RISC-V specification has been contributed to directly or indirectly by:

  • Iain Robertson - author

  • Robert Chyla (MIPS)

  • Ved Shanbhogue (Meta)

HART Trace Interface Introduction
riscv.org Technical Hub Code of Conduct Privacy Policy Join RISC-V

Copyright © RISC-V International®. All rights reserved. RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International.