RISCV RISCV
Home Home
  • RISC-V Specifications
System Architecture
    • Advanced Interrupt Architecture
      • Contributors
      • Preface
      • Copyright
      • Introduction
      • Chapter 1. CSRs Added to Harts
      • Chapter 2. Incoming MSI Controller (IMSIC)
      • Chapter 3. Advanced PLIC (APLIC)
      • Chapter 4. Interrupts for Machine and Supervisor Levels
      • Chapter 5. Interrupts for Virtual Machines (VS Level)
      • Chapter 6. Interprocessor Interrupts (IPIs)
      • Chapter 7. IOMMU Support for MSIs to Virtual Machines
    • IOMMU
      • Copyright and License Information
      • Contributors
      • Introduction
      • Data Structures
      • In-memory Queue Interface
      • Debug Support
      • Memory-mapped Register Interface
      • Software Guidelines
      • Hardware Guidelines
      • Bibliography
    • Platform-Level Interrupt Controller
      • Changelog
      • Copyright and license
      • Contributors
      • Introduction
      • Chapter 1. RISC-V PLIC Operation Parameters
      • Chapter 2. Memory Map
      • Chapter 3. Interrupt Priorities
      • Chapter 4. Interrupt Pending Bits
      • Chapter 5. Interrupt Enables
      • Chapter 6. Priority Thresholds
      • Chapter 7. Interrupt Claim Process
      • Chapter 8. Interrupt Completion
    • Server SoC
      • Copyright and License
      • Contributors
      • Introduction
      • Chapter 1. Server SoC Requirements
      • Chapter 2. Bibliography
Report a Problem GitHub Project More Details Download PDF
  • RISC-V Specifications
  • System Architecture Overview
  • RISC-V IOMMU

For the latest stable version, please use IOMMU 20260222!

RISC-V IOMMU Architecture Specification

RISCV

RISC-V IOMMU Architecture Specification

IOMMU Task Group

Version 1.0, 06/2023

This document is in the Ratified state

No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised.
Copyright and License Information
riscv.org Technical Hub Code of Conduct Privacy Policy Join RISC-V

Copyright © RISC-V International®. All rights reserved. RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International.