Table 1 lists both the CSRs added for machine level and existing machine-level CSRs whose size is changed by the Advanced Interrupt Architecture. Existing CSRs mie, mip, and mideleg are widened to 64 bits to support a total of 64 interrupt causes.

For RV32, the high-half CSRs listed in the table allow access to the upper 32 bits of registers mideleg, mie, mvien, mvip, and mip. The Advanced Interrupt Architecture requires that these high-half CSRs exist for RV32, but the bits they access may all be merely read-only zeros.

CSRs miselect and mireg provide a window for accessing multiple registers beyond the CSRs in Table 1. The value of miselect determines which register is currently accessible through alias CSR mireg. miselect is a WARL register, and it must support a minimum range of values depending on the implemented features. When an IMSIC is not implemented, miselect must be able to hold at least any 6-bit value in the range 0 to 0x3F. When an IMSIC is implemented, miselect must be able to hold any 8-bit value in the range 0 to 0xFF. The Advanced Interrupt Architecture makes use of these subranges of values for miselect:

Values of miselect with the most-significant bit set (bit XLEN - 1 = 1) are designated for custom use, presumably for accessing custom registers through mireg. If XLEN changes, the most-significant bit of miselect moves to the new position, retaining its value from before. An implementation is not required to support any custom values for miselect.

Other miselect values are reserved for other RISC-V extensions.

Normally, the range for external interrupts, 0x70-0xFF, is populated only when an IMSIC is implemented; else, attempts to access mireg when miselect is in this range cause an illegal instruction exception. The contents of the external-interrupts region are documented in Incoming MSI Controller (IMSIC) on the IMSIC.

CSR mtopei also exists only when an IMSIC is implemented, so is documented in Incoming MSI Controller (IMSIC) along with the indirectly accessed IMSIC registers.

CSR mtopi reports the highest-priority interrupt that is pending and enabled for machine level, as specified in Machine top interrupt CSR (mtopi).

When S-mode is implemented, CSRs mvien and mvip support interrupt filtering and virtual interrupts for supervisor level. These facilities are explained in Interrupt filtering and virtual interrupts for supervisor level.

If extension Smcsrind is also implemented, then when miselect has a value in the range 0x30-0x3F or 0x70-0xFF, attempts to access alias CSRs mireg2 through mireg6 raise an illegal instruction exception.

Table 2 lists the supervisor-level CSRs that are added and existing CSRs that are widened to 64 bits, if the hart implements S-mode. The functions of these registers all match their machine-level counterparts.

The space of registers accessible through the siselect/sireg window is separate from but parallels that of machine level, being for supervisor-level interrupts instead of machine-level interrupts. The subranges of values used for siselect are once again these:

For maximum compatibility, it is recommended that siselect support at least a 9-bit range, 0 to 0x1FF, regardless of whether an IMSIC exists.

Like miselect, values of siselect with the most-significant bit set (bit XLEN - 1 = 1) are designated for custom use. If XLEN changes, the most-significant bit of siselect moves to the new position, retaining its value from before. An implementation is not required to support any custom values for siselect.

Other siselect values are reserved for other RISC-V extensions.

Note that the widths of 'siselect' and 'sireg' are always the current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and SXLEN = 32, then these registers are 64 bits when the current privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).

CSR stopei is described with the IMSIC in Incoming MSI Controller (IMSIC).

Register stopi reports the highest-priority interrupt that is pending and enabled for supervisor level, as specified in Supervisor top interrupt CSR (stopi).

If extension Sscsrind is also implemented, then when siselect has a value in the range 0x30-0x3F or 0x70-0xFF, attempts to access alias CSRs sireg2 through sireg6 raise an illegal instruction exception (unless executing in a virtual machine, covered in the next section).

If a hart implements the H extension, then the hypervisor and VS CSRs listed in Table 3 are also either added or widened to 64 bits.

The new hypervisor CSRs in the table (hvien, hvictl , hviprio1, and hviprio2) augment hvip for injecting interrupts into VS level. The use of these registers is covered in Interrupts for Virtual Machines (VS Level) on interrupts for virtual machines.

The new VS CSRs (vsiselect, vsireg, vstopei, and vstopi) all match supervisor CSRs, and substitute for those supervisor CSRs when executing in a virtual machine (in VS-mode or VU-mode).

CSR vsiselect is required to support at least a 9-bit range of 0 to 0x1FF, whether or not an IMSIC is implemented. As with siselect, values of vsiselect with the most-significant bit set (bit XLEN - 1 = 1) are designated for custom use. If XLEN changes, the most-significant bit of vsiselect moves to the new position, retaining its value from before.

Like siselect and sireg, the widths of vsiselect and vsireg are always the current XLEN rather than VSXLEN. Hence, for example, if HSXLEN = 64 and VSXLEN = 32, then these registers are 64 bits when accessed by a hypervisor in HS-mode (running RV64 code) but 32 bits for a guest OS in VS-mode (RV32 code).

The space of registers selectable by vsiselect is more limited than for machine and supervisor levels:

Other vsiselect values are reserved for other RISC-V extensions.

For alias CSRs sireg and vsireg, the H extension’s usual rules for when to raise a virtual instruction exception (based on whether an instruction is HS-qualified) are not applicable. The rules given in this section for sireg and vsireg apply instead, unless overridden by the requirements of 2.1.5. Access control by the state-enable CSRs, which take precedence over this section when extension Smstateen is also implemented.

A virtual instruction exception is raised for attempts from VS-mode or VU-mode to directly access vsireg, or attempts from VU-mode to access sireg.

When vsiselect has the number of an inaccessible register, attempts from M-mode or HS-mode to access vsireg raise an illegal instruction exception, and attempts from VS-mode to access sireg (really vsireg) raise a virtual instruction exception.

The indirectly accessed registers for external interrupts (numbers 0x70-0xFF) are accessible only when field VGEIN of hstatus is the number of an implemented guest external interrupt, not zero. If VGEIN is not the number of an implemented guest external interrupt (including the case when no IMSIC is implemented), then all indirect register numbers in the ranges 0x030-0x03F and 0x070-0x0FF designate an inaccessible register at VS level.

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction exception, and attempts from VS-mode to access stopei raise a virtual instruction exception.

If extension Sscsrind is also implemented, then when vsiselect has a value in the range 0x30-0x3F or 0x70-0xFF, attempts from M-mode or HS-mode to access alias CSRs vsireg2 through vsireg6 raise an illegal instruction exception, and attempts from VS-mode to access sireg2 through sireg6 raise a virtual instruction exception.

Following the default rules for the H extension, attempts from VS-mode to directly access a hypervisor or VS CSR other than vsireg, or from VU-mode to access any supervisor-level CSR (including hypervisor and VS CSRs) other than sireg or vsireg, usually raise not an illegal instruction exception but instead a virtual instruction exception. For details, see the H extension documentation.

Instructions that read/write CSR stopei or vstopei are considered to be HS-qualified unless all of following are true: the hart has an IMSIC, extension Smstateen is implemented, and bit 58 of mstateen0 is zero. (See the next section, 2.1.5. Access control by the state-enable CSRs, about mstateen0.)

For sireg and vsireg, see both the previous section, 2.1.3. Hypervisor and VS CSRs, and the next, 2.1.5. Access control by the state-enable CSRs, for when a virtual instruction exception is required instead of an illegal instruction exception.

If extension Smstateen is implemented together with the Advanced Interrupt Architecture (AIA), three bits of state-enable register mstateen0 control access to AIA-added state from privilege modes less privileged than M-mode:

If one of these bits is zero in mstateen0, an attempt to access the corresponding state from a privilege mode less privileged than M-mode results in an illegal instruction trap. As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less privileged modes. For more explanation, see the documentation for extension Smstateen.

The AIA bit controls access to AIA CSRs siph, sieh, stopi, hidelegh, hvien/hvienh, hviph, hvictl, hviprio1/hviprio1h, hviprio2/hviprio2h, vsiph, vsieh, and vstopi, as well as to the supervisor-level interrupt priorities accessed through siselect + sireg (the iprio array of Configuring priorities of major interrupts at supervisor level).

The IMSIC bit is implemented in mstateen0 only if the hart has an IMSIC. If the H extension is also implemented, this bit does not affect the behavior or accessibility of hypervisor CSRs hgeip and hgeie, or field VGEIN of hstatus. In particular, guest external interrupts from an IMSIC continue to be visible to HS-mode in hgeip even when mstateen0.IMSIC is zero.

If the hart does not have an IMSIC, the IMSIC bit of mstateen0 is read-only zero, but Smstateen has no effect on attempts to access the nonexistent IMSIC state.

If the CSRIND bit of mstateen0 is one, then regardless of any other mstateen bits (including the AIA and IMSIC bits of mstateen0), a virtual instruction exception is raised as described in 2.1.3. Hypervisor and VS CSRs for all attempts from VS-mode or VU-mode to directly access vsireg, and for all attempts from VU-mode to access sireg. This behavior is overridden only when mstateen0.CSRIND is zero.

If the H extension is implemented, the same three bits are defined also in hypervisor CSR hstateen0 but concern only the state potentially accessible to a virtual machine executing in privilege modes VS and VU:

If one of these bits is zero in hstateen0, and the same bit is one in mstateen0, then an attempt to access the corresponding state from VS or VU-mode raises a virtual instruction exception. (But note that, for high-half CSRs siph and sieh, this applies only when XLEN = 32. When XLEN > 32, an attempt to access siph or sieh raises an illegal instruction exception as usual, not a virtual instruction exception.)

If the CSRIND bit is one in mstateen0 but is zero in hstateen0, then all attempts from VS or VU-mode to access siselect or sireg raise a virtual instruction exception, not an illegal instruction exception, regardless of the value of vsiselect or any other mstateen bits.

The IMSIC bit is implemented in hstateen0 only if the hart has an IMSIC. Furthermore, even with an IMSIC, hstateen0.IMSIC may (or may not) be read-only zero if the IMSIC has no guest interrupt files for guest external interrupts (Incoming MSI Controller (IMSIC)). When this bit is zero (whether read-only zero or set to zero), a virtual machine is prevented from accessing the hart’s IMSIC the same as when hstatus.VGEIN = 0.

Extension Ssstateen is defined as the supervisor-level view of Smstateen. Therefore, the combination of Ssaia and Ssstateen incorporates the bits defined above for hstateen0 but not those for mstateen0, since machine-level CSRs are not visible to supervisor level.