Preface

This document describes an Advanced Interrupt Architecture (AIA) for RISC-V systems. This specification was ratified by the RISC-V International Association in June of 2023.

The table below indicates which chapters of this document specify extensions to the RISC-V ISA (instruction set architecture) and which are non-ISA.

Chapter ISA?

1. Introduction

—

2. Control and Status Registers (CSRs) Added to Harts

Yes

3. Incoming MSI Controller (IMSIC)

Yes

4. Advanced Platform-Level Interrupt Controller (APLIC)

No

5. Interrupts for Machine and Supervisor Levels

Yes

6. Interrupts for Virtual Machines (VS Level)

Yes

7. Interprocessor Interrupts (IPIs)

No

8. IOMMU Support for MSIs to Virtual Machines

No

Changes for version 20250312

Made the following clarifications to AIA 1.0:

  • Where there are irreconcilable conflicts between the AIA and other implemented RISC-V extensions, the AIA usually has priority by default.

  • Deference is given to extension Smcsrind/Sscsrind (indirectly accessed CSRs).

  • Names are given to the bits defined in mstateen0 and hstateen0 when extension Smstateen/Ssstateen is also implemented.

  • An IMSIC interrupt file’s eidelivery register affects only whether an interrupt appears in a hart’s mip or hgeip register.

  • IMSIC CSRs mtopei, stopei, and vstopei are not affected by the values of mie, sie, hie, hgeie, or vsie.

  • There may be a visible delay between a change of state of an IMSIC interrupt file and its effect on a bit in mip, sip, or hgeip.

  • An APLIC’s idelivery registers and the IE bits of its domaincfg registers affect only whether pending-and-enabled interrupts are delivered to harts.

  • The default priority order for major interrupts is applicable only when multiple interrupts would trap to the same privilege mode.

  • The example pseudocode given for handling major interrupts at M-level and S-level has additional requirements not mentioned previously.

  • An interrupt priority number in the S-level iprio array may be writable (not read-only zero) if the correponding bit is writable in either sie or hie.

  • If a supervisor external interrupt (SEI) is injected from M-level when there is no actual interrupt from an external interrupt controller, the injected SEI is assigned an S-level priority number of 256.

  • CSR hvictl affects only vstopi and the trapping of some instructions, not mip, sip, hip, or vsip.

Changes for the ratified version 1.0

Resolved some inconsistencies in Control and Status Registers (CSRs) Added to Harts about when to raise a virtual instruction exception versus an illegal instruction exception.

Changes for RC5 (Release Candidate 5)

Better aligned the rules for indirectly accessed registers with the hypervisor extension and with forthcoming extension Smcsrind/Sscsrind. In particular, when vsiselect has a reserved value, attempts to access sireg from a virtual machine (VS or VU-mode) should preferably raise an illegal instruction exception instead of a virtual instruction exception.

Added clarification about the term IOMMU used in IOMMU Support for MSIs to Virtual Machines.

Added clarification about MSI write replaced by MRIF update and notice MSI sent after the update.

Changes for RC4

For alignment with other forthcoming RISC-V ISA extensions, the widths of the indirect-access CSRs, miselect, mireg, siselect, sireg, vsiselect, and vsireg, were changed to all be the current XLEN rather than being tied to their respective privilege levels (previously MXLEN for miselect and mireg, SXLEN for siselect and sireg, and VSXLEN for vsiselect and vsireg).

Changed the description (but not the actual function) of high-half CSRs and their partner CSRs to match the latest RISC-V Privileged ISA specification. (An example of a high-half CSR is miph, and its partner here is mip.)

Changes for RC3

Removed the still-draft Duo-PLIC chapter to a separate document.

Allocated major interrupts 35 and 43 for signaling RAS events (Defined major interrupts and default priorities).

In Interrupt filtering and virtual interrupts for supervisor level added the options for bits 1 and 9 to be writable in CSR mvien, and specified the effects of setting each of these bits.

Upgraded IOMMU Support for MSIs to Virtual Machines ("IOMMU Support") to the frozen state.

Changes for RC2

Clarified that field IID of CSR hvictl must support all unsigned integer values of the number of bits implemented for that field, and that writes to hvictl always set IID in the most straightforward way.

A comment was added to Interprocessor Interrupts (IPIs) warning about the possible need for FENCE instructions when IPIs are sent to other harts by writing MSIs to those harts' IMSICs.