Ratified version

Remove H/U mode from this spec.

Clarify the "register width" when access to memory map register.

Combine Register Width chapter and Memory Map chapter.

Update specification to Frozen state.

Revised Copyright and license information

Added Andrew Waterman and Krste Asanovic as contributors who did the original design and wrote the spec.

Revised the copyright statements to follow section 3.3 in Appendix A "INTELLECTUAL PROPERTY RIGHTS POLICY " of the RISC-V Regulations.

Correct offsets of PLIC Interrupt Enable Bits memory map.

The pre-public review version