Quality of Service (QoS) is defined as the minimal end-to-end performance guaranteed in advance by a service level agreement (SLA) to a workload. Performance metrics might include measures such as instructions per cycle (IPC), latency of service, etc.

When multiple workloads execute concurrently on modern processors — equipped with large core counts, multiple cache hierarchies, and multiple memory controllers — the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention [10].

To manage performance variability, system software needs resource allocation and monitoring capabilities. These capabilities allow for the reservation of resources like cache and bandwidth, thus meeting individual performance targets while minimizing interference [11]. For resource management, hardware should provide monitoring features that allow system software to profile workload resource consumption and allocate resources accordingly.

To facilitate this, the QoS Identifiers ISA extension (Ssqosid) [12] introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers.

These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller QoS Register Interface [13], which provides methods for setting resource usage limits and monitoring resource consumption. The RCID controls resource allocations, while the MCID is used for tracking resource usage.

The IOMMU QoS ID extension provides a method to associate QoS IDs with requests to access resources by the IOMMU, as well as with devices governed by it. This complements the Ssqosid extension that provides a method to associate QoS IDs with requests originated by the RISC-V harts. Assocating QoS IDs with device and IOMMU originated requests is required for effective monitoring and allocation of shared resources.

The IOMMU capabilities register (iommu_registers.adoc#CAP) is extended with a QOSID field which enumerates support for associating QoS IDs with requests made through the IOMMU. When capabilities.QOSID is 1, the memory-mapped register layout is extended to add a register named iommu_qosid (iommu_registers.adoc#IOQOSID). This register is used to configure the Quality of Service (QoS) IDs associated with IOMMU-originated requests. The ta field of the device context (iommu_data_structures.adoc#DC_TA) is extended with two fields, RCID and MCID, to configure the QoS IDs to associate with requests originated by the devices.

The RISC-V IOMMU Version 1.0 specification provides commands to invalidate leaf page table entries from address translation caches when performing an address-specific invalidation operation. The non-leaf PTE invalidation extension provides commands to optionally also invalidate non-leaf PTE entries from the address translation caches when performing an address-specific invalidation operation.

The non-leaf PTE invalidation extension is implemented if the capabilities.NL (bit 42) is 1. When the capabilities.NL bit is 1, a non-leaf (NL) field is defined at bit 34 in the IOTINVAL.VMA and IOTINVAL.GVMA commands by this extension. When the capabilities.NL bit is 0, bit 34 remains reserved.

If the address range invalidation extension is also implemented, the NL operand applies to the address range determined by the ADDR and S operands.

The address range invalidation extension enables specifying a range of addresses in an IOMMU ATC invalidation command, reducing the number of commands queued to the IOMMU. This facility is especially useful when superpages are employed in page tables.

The address range invalidation extension is implemented if capabilities.S (bit 43) is 1. When capabilities.S is 1, a range-size (S) operand is defined at bit 73 in the IOTINVAL.VMA and IOTINVAL.GVMA commands by this extension. When the capabilities.S bit is 0, bit 73 remains reserved.

When the GV operand is 0, both the AV and S operands are ignored by the IOTINVAL.GVMA command. When the AV operand is 0, the S operand is ignored in both the IOTINVAL.VMA and IOTINVAL.GVMA commands. When the S operand is ignored or set to 0, the operations of the IOTINVAL.VMA and IOTINVAL.GVMA commands are as specified in the RISC-V IOMMU Version 1.0 specification.

When the S operand is not ignored and is 1, the ADDR operand represents a NAPOT range encoded in the operand itself. Starting from bit position 0 of the ADDR operand, if the first 0 bit is at position X, the range size is 2(X+1) * 4 KiB. When X is 0, the size of the range is 8 KiB.

If the S operand is not ignored and is 1 and all bits of the ADDR operand are 1, the behavior is UNSPECIFIED.

If the S operand is not ignored and is 1 and the most significant bit of the ADDR operand is 0 while all other bits are 1, the specified address range covers the entire address space.

The Svrsw60t59b extension is implemented if capabilities.Svrsw60t59b (bit 14) is set to 1.