[1] Clarification updates to IOMMU v20250828. [Online]. Available: https://github.com/riscv-non-isa/riscv-iommu/pull/617/commits

[2] Clarification updates to IOMMU v20250625. [Online]. Available: https://github.com/riscv-non-isa/riscv-iommu/pull/569/commits

[3] Clarification updates to IOMMU v1.0.1. [Online]. Available: https://github.com/riscv-non-isa/riscv-iommu/pull/441/commits

[4] Clarification updates to IOMMU v1.0.0. [Online]. Available: https://github.com/riscv-non-isa/riscv-iommu/pull/243/commits

[5] PCI Express® Base Specification Revision 6.0, . [Online]. Available: https://pcisig.com/pci-express-6.0-specification

[6] RISC-V Advanced Interrupt Architecture. [Online]. Available: https://github.com/riscv/riscv-aia

[7] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, . [Online]. Available: https://github.com/riscv/riscv-isa-manual

[8] RISC-V Shadow Stacks and Landing Pads. [Online]. Available: https://github.com/riscv/riscv-cfi

[9] PCI Code and ID Assignment Specification Revision 1.1, . [Online]. Available: https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf

[10] D. B. Kristof and E. Stijn and E. Lieven, "Per-Thread Cycle Accounting in Multicore Processors", ACM Trans. Archit. Code Optim., vol. 9, no. 4, jan 2013. [Online]. Available: https://doi.org/10.1145/2400682.2400688.

[11] L. David and C. Liqun and G. Rama and R. Parthasarathy and K. Christos, "Heracles: Improving Resource Efficiency at Scale" in Proceedings of the 42nd Annual International Symposium on Computer Architecture, ISCA '15. New York, NY, USA:, Association for Computing Machinery, 2015, pp. 450–462, Available: https://doi.org/10.1145/2749469.2749475.

[12] RISC-V Quality-of-Service (QoS) Identifiers. [Online]. Available: https://github.com/riscv/riscv-ssqosid

[13] RISC-V Capacity and Bandwidth QoS Register Interface. [Online]. Available: https://github.com/riscv-non-isa/riscv-cbqri