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  • RISC-V Specifications
Application Enablement
    • ABIs Specification
      • Preamble
      • Introduction
      • Terms and Abbreviations
      • Status of ABI
  • RISC-V Calling Conventions
    • Chapter 1. Register Convention
    • Chapter 2. Procedure Calling Convention
    • Chapter 3. Calling Conventions for System Calls
    • Chapter 4. C/C++ type details
    • Appendix A. Linux-specific ABI
  • RISC-V ELF Specification
    • Chapter 5. Code Models
    • Chapter 6. Dynamic Linking
    • Chapter 7. C++ Name Mangling
    • Chapter 8. ELF Object Files
    • Chapter 9. Linker Relaxation
    • References
  • RISC-V DWARF Specification
    • Chapter 10. DWARF Debugging Format
    • Chapter 11. DWARF Register Numbers
    • References
    • Vector C Intrinsic
      • Copyright and license information
      • Contributors
      • Introduction
      • Chapter 1. Examples
      • Appendix A: Explicit (Non-overloaded) intrinsics
        • Vector Loads and Stores Intrinsics
        • A.1. Vector Loads and Stores Segment Intrinsics
        • A.2. Vector Integer Arithmetic Intrinsics
        • A.3. Vector Fixed-Point Arithmetic Intrinsics
        • A.4. Vector Floating-Point Intrinsics
        • A.5. Vector Reduction Operations
        • A.6. Vector Mask Intrinsics
        • A.7. Vector Permutation Intrinsics
        • A.8. Miscellaneous Vector Utility Intrinsics
      • Appendix B: Explicit (Non-overloaded) intrinsics, policy variants
        • B.1. Vector Loads and Stores Intrinsics
        • B.2. Vector Loads and Stores Segment Intrinsics
        • B.3. Vector Integer Arithmetic Intrinsics
        • B.4. Vector Fixed-Point Arithmetic Intrinsics
        • B.5. Vector Floating-Point Intrinsics
        • B.6. Vector Reduction Operations
        • B.7. Vector Mask Intrinsics
        • B.8. Vector Permutation Intrinsics
        • B.9. Miscellaneous Vector Utility Intrinsics
      • Appendix C: Implicit (Overloaded) intrinsics
        • C.1. Vector Loads and Stores Intrinsics
        • C.2. Vector Loads and Stores Segment Intrinsics
        • C.3. Vector Integer Arithmetic Intrinsics
        • C.4. Vector Fixed-Point Arithmetic Intrinsics
        • C.5. Vector Floating-Point Intrinsics
        • C.6. Vector Reduction Operations
        • C.7. Vector Mask Intrinsics
        • C.8. Vector Permutation Intrinsics
        • C.9. Miscellaneous Vector Utility Intrinsics
      • Appendix D: Implicit (Overloaded) intrinsics, policy variants
        • D.1. Vector Loads and Stores Intrinsics
        • D.2. Vector Loads and Stores Segment Intrinsics
        • D.3. Vector Integer Arithmetic Intrinsics
        • D.4. Vector Fixed-Point Arithmetic Intrinsics
        • D.5. Vector Floating-Point Intrinsics
        • D.6. Vector Reduction Operations
        • D.7. Vector Mask Intrinsics
        • D.8. Vector Permutation Intrinsics
        • D.9. Miscellaneous Vector Utility Intrinsics
      • Bibliography
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  • RISC-V Specifications
  • Application Enablement Overview
  • Vector C Intrinsic

Contributors

Contributors

This RISC-V specification has been contributed to directly or indirectly by (in alphabetical order):

Contributors to all versions of the spec in alphabetical order:

Brandon Wu, Craig Topper, Eop Chen, HanKuan Chen, HsiangKai Wang, Jerry Zhang Jian, Kito Cheng, Nick Knight, Olaf Bernstein, Roger Ferrer Ibanez, Yi-Hsiu Hsu, Zakk Chen

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