Bibliography
[1] D. B. Kristof and E. Stijn and E. Lieven, "Per-Thread Cycle Accounting in Multicore Processors", ACM Trans. Archit. Code Optim., vol. 9, no. 4, jan 2013. [Online]. Available: https://doi.org/10.1145/2400682.2400688.
[2] L. David and C. Liqun and G. Rama and R. Parthasarathy and K. Christos, "Heracles: Improving Resource Efficiency at Scale" in Proceedings of the 42nd Annual International Symposium on Computer Architecture, ISCA '15. New York, NY, USA:, Association for Computing Machinery, 2015, pp. 450–462, Available: https://doi.org/10.1145/2749469.2749475.
[3] RISC-V Quality-of-Service (QoS) Identifiers. [Online]. Available: https://github.com/riscv/riscv-ssqosid
[4] RISC-V State Enable Extension. [Online]. Available: https://drive.google.com/file/d/1dhI6OzVbejQbfwyBTuwK9U4VUmW8ii4o/view
[5] RISC-V IOMMU Architecture Specification. [Online]. Available: https://github.com/riscv-non-isa/riscv-iommu