There are two standard RISC-V trace protocols which will utilize this RISC-V Trace Control Interface:

This specification together with details provided in any of above documents should be considered as a complete guideline for any standard RISC-V trace implementation.

Trace is controlled by set of 32-bit memory-mapped registers.

Not all trace protocols and components must support all registers, bits, fields and options. This document includes a chapter Minimal Implementation which describes the smallest possible set of registers and fields, but each message protocol supported by this standard must clarify the exact meaning of supported registers/fields and bits as some of them define.