Untitled :: RISC-V Ratified Specifications Library

Trace Encoder Control Interface

Many features of the Trace Encoder (TE for short) are optional. In most cases, optional features are enabled using a WARL (write any, read legal) register field. A debugger can determine if optional feature is present by writing to the register field and reading back the result.

Table 1. **Register: trTeControl: Trace Encoder Control Register (trBaseEncoder+0x000)**
Bit	Field	Description	RW	Reset
0	trTeActive	Primary activate/reset bit for the TE. When 0, the TE may have clocks gated off or be powered down, and other register locations may be inaccessible. Hardware may take an arbitrarily long time to process power-up and power-down and will indicate completion when the read value of this bit matches what was written. See Reset and Discovery chapter for more details.	RW	0
1	trTeEnable	1: Trace Encoder is enabled. Allows `trTeInstTracing` and `trTeDataTracing` to turn tracing on and off. Setting `trTeEnable` to 0 flushes any queued trace data to the sink or funnel attached to this encoder. This bit can be set to 1 only by direct writing to it. This write of 1 should be done after all other settings are done. See Enabling and Disabling chapter for more details.	RW	0
2	trTeInstTracing	1: Instruction trace is being generated. Written from a trace tool (after a write to `trTeEnable`) or controlled by triggers. When `trTeInstTracing=1`, instruction trace data may be subject to additional filtering in some implementations (additional `trTeInstMode` settings).	RW	Undef
3	trTeEmpty	Reads as 1 when all generated trace have been emitted.	RO	1
6:4	trTeInstMode	Instruction trace generation mode 0: Full Instruction trace is disabled, but other trace (data trace) may be emitted. 1-2: Protocol defined trace mode. 3: Baseline instruction trace (for example Branch Trace). 4-5: Protocol defined trace mode. 6: Optimized instruction trace (for example Branch History Trace). 7: Reserved for vendor-defined instruction trace mode. NOTE: When non-supported mode (different than 0) is set, it cannot revert to 0 but MUST revert to supported non-0 mode.	WARL	Undef
8:7	—	Reserved	—	0
9	trTeContext	Enable sending trace messages/fields with scontext/mcontext values and/or privilege levels.	WARL	Undef
10	—	Reserved	—	0
11	trTeInstTrigEnable	1: Allows `trTeInstTracing` to be set or cleared by Trace-on and Trace-off signals generated by the corresponding trigger module.	WARL	Undef
12	trTeInstStallOrOverflow	Set to 1 by hardware when trace buffer overflow (also known as trace lost) occurs, or when the TE requests a hart stall. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear.	RW1C	Undef
13	trTeInstStallEna	0: If TE cannot send a message, the message is dropped. The protocol dependent overflow instruction trace synchronization message/packet is generated when the trace is restarted, so the decoder will know that trace is lost and must reset any internal decoder state. 1: If TE cannot send a message, the hart is stalled until it can. With this option execution of instructions by the hart may be intrusively affected, but in many cases it is acceptable.	WARL	Undef
14	—	Reserved	—	0
15	trTeInhibitSrc	0: Messages/packets generated by the trace encoder include a message source field if the source width held in `trTeSrcBits` is not 0. 1: Disable inclusion of source field in trace messages/packets.	WARL	Undef
17:16	trTeInstSyncMode	Select the periodic instruction trace synchronization message/packet generation mechanism. At least one non-zero mechanism must be implemented. 0: Off 1: Count trace messages/packets 2: Count hart clock cycles 3: Count instruction 16-bit half-words Once the max value of periodic counter is reached, an instruction trace synchronization message/packet should be generated.	WARL	Undef
19:18	—	Reserved	—	0
23:20	trTeInstSyncMax	The maximum interval (in units determined by `trTeInstSyncMode`) between instruction trace synchronization messages/packets. Generate synchronization when count reaches 2^(`trTeInstSyncMax`+4). If an instruction trace synchronization message/packet is generated for another reason, the internal counter should be reset.	WARL	Undef
26:24	trTeFormat	Trace recording/protocol format: 0: Format defined by Efficient Trace for RISC-V (E-Trace) Specification 1: Format defined by RISC-V N-Trace (Nexus-based Trace) Specification 2-6: Reserved for future formats 7: Vendor-specific format	WARL	Undef
31:27	—	Reserved	—	0

Writing to this register while trace is enabled may unintentionally change a value of trTeInstTracing bit because that bit may dynamically change by triggers.

Table 2. **Register: trTeImpl: Trace Encoder Implementation Register (trBaseEncoder+0x004)**
Bit	Field	Description	RW	Reset
3:0	trTeVerMajor	Trace Encoder Component Major Version. Value 1 means the component is compliant with this document. Value 0 means pre-ratified/initial version - see 'Pre-ratified/Initial Interface Version' chapter at the end.	RO	1
7:4	trTeVerMinor	Trace Encoder Component Minor Version. Value 0 means the component is compliant with this document.	RO	0
11:8	trTeCompType	Trace Encoder Component Type (Trace Encoder)	RO	0x1
15:12	—	Reserved for future versions of this standard	—	0
19:16	trTeProtocolMajor	Trace Protocol Major Version. As specified by specification governing `trTeFormat`.	RO	SD
23:20	trTeProtocolMinor	Trace Protocol Minor Version. As specified by specification governing `trTeFormat`.	RO	SD
31:24	—	Reserved for vendor specific implementation details	—	SD

trTeProtocol?? fields are separated from trTeVer?? as we may have the same control interface, but protocol itself may be extended with new packets/ messages/ fields.

Table 3. **Register: trTeInstFeatures: Trace Instruction Features Register (trBaseEncoder+0x008)**
Bit	Field	Description	RW	Reset
0	trTeInstNoAddrDiff	When set, trace messages/packets always carry a full address.	WARL	Undef
1	trTeInstNoTrapAddr	When set, do not include trap handler address in trap messages/packets.	WARL	Undef
2	trTeInstEnSequentialJump	When set, treat sequentially inferrable jumps as inferable PC discontinuities.	WARL	Undef
3	trTeInstEnImplicitReturn	When set, treat returns as inferable PC discontinuities when returning from a recent call on a stack. Field `trTeInstImplicitReturnMode` below provides more details.	WARL	Undef
4	trTeInstEnBranchPrediction	When set, Branch Predictor based compression is enabled.	WARL	Undef
5	trTeInstEnJumpTargetCache	When set, Jump Target Cache based compression is enabled.	WARL	Undef
7:6	trTeInstImplicitReturnMode	Defines how the decoder is handling stack of return addresses (if enabled by `trTeInstEnImplicitReturn` bit): 0: Implicit Return mode is not supported, or implementation is not reporting how it is implemented. 1: Simple level counting without the return address comparing. 2: Partial (LSB portion of return address) compare (smaller logic cost than 3 below, but in most cases adequate as chances to have an incorrect return address with same LSB bits is very slim). 3: Full address comparing (always assures skipped return addresses are the same as addresses deducted from call instruction). Implementation may take advantage of RAS (Return Address Stack) if implemented by the hart.	WARL	Undef
8	trTeInstEnRepeatedHistory	Enable repeated branch history/map detection when set.	WARL	Undef
9	trTeInstEnAllJumps	Enable emitting of trace message or add history/map bit for direct unconditional/inferable control flow changes (jumps or calls). Normally these instructions do not generate any trace as the decoder can determine the next instruction. Trace will not compress well but timestamp accuracy will be better - may be used when profiling loops.	WARL	Undef
10	trTeInstExtendAddrMSB	When set, allow extended handing of MSB address bits. Encoding details are trace protocol dependent.	WARL	Undef
15:11	—	Reserved for additional instruction trace control/status bits	—	0
27:16	trTeSrcID	Trace source ID assigned to this trace encoder. If `trTeSrcBits` is not 0 and trace source is not disabled by `trTeInhibitSrc`, then trace messages from this TE will all include a trace source field of `trTeSrcBits` bits and all messages from this TE will use this value as trace source field.	WARL	Undef
31:28	trTeSrcBits	The number of bits in the trace source field (0..12), unless disabled by `trTeInhibitSrc`. Some trace protocols may require that this field is identical for all enabled trace encoders within the same trace stream.	WARL	Undef

Applicability of different trTeInst?? fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols).

Table 4. **Register: trTeInstFilters: Trace Instruction Filters Register (trBaseEncoder+0x00C)**
Bit	Field	Description	RW	Reset
15:0	trTeInstFilters	Determine which filters defined in Trace Encoder Filter Registers chapter qualify an instruction trace. If bit n is a 1 then instructions will be traced when filter n matches. If all bits are 0, all instructions are traced.	WARL	Undef
31:16	—	Reserved	—	0

Table 5. **Register: trTeDataControl: Data Trace Control Register (trBaseEncoder+0x010)**
Bit	Field	Description	RW	Reset
0	trTeDataImplemented	Read as 1 if data trace is implemented.	RO	SD
1	trTeDataTracing	1: Data trace is being generated. Written from a trace tool or controlled by triggers. When `trTeDataTracing`=1, data trace may be subject to additional filtering in some implementations.	WARL	Undef
2	trTeDataTrigEnable	Global enable/disable for data trace triggers	WARL	Undef
3	trTeDataStallOrOverflow	Set to 1 by hardware when data trace causes trace buffer overflow, or when the TE requests a hart stall due to data trace. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear.	RW1C	Undef
4	trTeDataStallEna	0: If TE cannot send data trace messages, an overflow message is generated when the trace is restarted. 1: If TE cannot send data trace messages, the hart is stalled until it can.	WARL	Undef
5	trTeDataDrop	Written to 1 by hardware when the data trace packet was dropped (if enabled). Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear.	RW1C	Undef
6	trTeDataDropEna	1: Allow temporary suppression of data trace (at some watermark level) to prevent trace overflow or stall. This way instruction trace will have higher priority.	WARL	Undef
15:7	—	Reserved for additional data trace control/status bits.	—	0
16	trTeDataNoValue	When set, omit data values from data trace packets.	WARL	Undef
17	trTeDataNoAddr	When set, omit data address from data trace packets.	WARL	Undef
19:18	trTeDataAddrCompress	Data trace address compression selection: 0: Only send full (unmodified) addresses 1: Use XOR compression 2: Use differential compression 3: Protocol defined address compression	WARL	Undef
31:20	—	Reserved	—	0

Writing to this register while trace is enabled may unintentionally change a value of trTeDataTracing bit because that bit may dynamically change by triggers.

Applicability of different trTeData?? fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols).

Table 6. **Register: trTeDataFilters: Trace Data Filters Register (trBaseEncoder+0x01C)**
Bit	Field	Description	RW	Reset
15:0	trTeDataFilters	Determine which filters defined in Trace Encoder Filter Registers chapter qualify data trace. If bit n is a 1 then data accessed will be traced when filter n matches. If all bits are 0, all data accesses are traced.	WARL	Undef
31:16	—	Reserved	—	0

Timestamp Unit

Timestamp Unit is an optional sub-component present in either Trace Encoder or Trace Funnel. An implementation may choose from several modes of timestamps:

Internal System - fixed clock in a system (such as bus clock) is used to increment the timestamp counter (for both Trace Encoders and Trace Funnels)
Internal Core - core clock is used to increment the timestamp counter (only for Trace Encoders)
Shared - shares timestamp with another Trace Encoder or Trace Funnel
External - accepts a binary timestamp value from an outside source such as ARM CoreSight™ trace (for both Trace Encoders and Trace Funnels)

Implementations may have no timestamp, one timestamp mode, or more than one mode. The WARL field trTsMode is used to determine the system capability and to set the desired timestamp mode.

The width of the timestamp is implementation dependent, typically 40 or 48 bits (40-bit timestamp will overflow every 4.7 minutes assuming 1GHz timestamp clock).

In a system with Funnels, typically all the Funnels are built with a Timestamp Unit. The top-level Funnel is the source of the timestamp (Internal System or External) and all the Encoders and other Funnels have a Shared timestamp. This assures that all timestamps in the system are the same and trace from different harts may be time-correlated. To perform the forwarding function, the mid-level Funnels must be programmed with trFunnelActive = 1 (which is natural as all trace messages must pass through that funnel).

An Internal System or Core timestamp unit may include a timestamp clock pre-scaler divider, which can extend the range of a narrower timestamp and uses less power but has less resolution.

In a system with an Internal Core timestamp counter (implemented in Trace Encoder associated with a hart) an optional control bit is provided to stop the counter when the hart is halted by a debugger.

Table 7. **Register: trBaseEncoder/Funnel+0x040 trTsControl: Timestamp Control Register**
Bit	Field	Description	RW	Reset
0	trTsActive	Primary activate/reset bit for timestamp unit. This must either be RW or, if separated reset for timestamp component is not implemented, a read-only copy of the corresponding `trTeActive` or `trFunnelActive` bit. See Reset and Discovery chapter for more details.	WARL	SD
1	trTsCount	Internal System or Core timestamp only. 1: counter runs, 0: counter stopped.	WARL	Undef
2	trTsReset	Internal System or Core timestamp only. Write 1 to reset the timestamp counter.	W1	—
3	trTsRunInDebug	Internal Core timestamp only. 1: counter runs when hart is halted (in debug mode), 0: stopped	WARL	Undef
6:4	trTsMode	Mode used by Timestamp unit: 0: None 1: External 2: Internal System 3: Internal Core 4: Shared 5-7: Vendor-specific mode	WARL	Undef
7	—	Reserved	—	0
9:8	trTsPrescale	Internal System or Core timestamp only. Prescale timestamp input clock by 2^(2*trTsPrescale). It will be divided by 1, 4, 16, 64 respectively.	WARL	Undef
14:10	—	Reserved	—	0
15	trTsEnable	Enable for timestamp field in trace messages/packets (for Trace Encoder only).	WARL	Undef
23:16		Vendor-specific bits to control what message/packet types include timestamp fields.	WARL	Undef
29:24	trTsWidth	Width of timestamp in bits (0..63)	RO	SD
31:30	—	Reserved	—	0

Table 8. **Register: trTsCounterLow: Timestamp Counter Lower Bits (trBaseEncoder/Funnel+0x048)**
Bit	Field	Description	RW	Reset
31:0	trTsCounterLow	Lower 32 bits of timestamp counter.	RO	0

Table 9. **Register: trTsCounterHigh: Timestamp Counter Upper Bits (trBaseEncoder/Funnel+0x04C)**
Bit	Field	Description	RW	Reset
31:0	trTsCounterHigh	Upper bits of timestamp counter, zero-extended.	RO	0

Trace Encoder Triggers

Debug Trigger Module

Debug module triggers are signals from the hart that a trigger was hit, but the action associated with that trigger is a trace-related action. Action identifiers 2-5 are reserved for trace actions in the RISC-V Debug Specification, where triggers are defined. Actions 2-4 are defined by the Efficient Trace for RISC-V (E-Trace) Specification. The desired action is written to the action field of the Match Control mcontrol CSR (0x7a1). As not all harts may support all trace actions, the debugger should read back the mcontrol CSR after setting the desired trace action to verify that the option exists.

Table 10. **Debug Trigger Actions**
Trigger Action (from debug spec)	Effect
0	Breakpoint exception (as defined in RISC-V Debug Specification)
1	Debug exception (as defined in RISC-V Debug Specification)
2	Trace-on action When `trTeInstTrigEnable` = 1 it will start instruction tracing (`trTeInstTracing` → 1). When `trTeDataTrigEnable` = 1 it will start data tracing (`trTeDataTracing` → 1).
3	Trace-off action When `trTeInstTrigEnable` = 1 it will stop instruction tracing (`trTeInstTracing` → 0). When `trTeDataTrigEnable` = 1 it will stop data tracing (`trTeDataTracing` → 0).
4	Trace-notify action If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packet with the current PC and, if enabled, a timestamp.
5	Vendor-specific trace action (optional)

If there are vendor-specific features that require control, the trTeTrigDbgControl register is used.

Table 11. **Register: trTeTrigDbgControl: Debug Trigger Control Register (trBaseEncoder+0x050)**
Bit	Field	Description	RW	Reset
31:0	trTeTrigDbgControl	Vendor-specific trigger setup	WARL	Undef

External Trace Triggers

The TE may be configured with up to 8 external trigger inputs for controlling trace. These are in addition to the external triggers present in the Debug Module when Halt Groups are implemented. The specific hardware signals comprising an external trigger are implementation dependent.

External Trigger Outputs may also be present. A trigger out may be generated by trace starting, trace stopping, a watchpoint, or by other system-specific events.

Table 12. **Register: trTeTrigExtInControl: External Trigger Input Control Register (trBaseEncoder+0x054)**
Bit	Field	Description	RW	Reset
3:0	trTeTrigExtInAction0	Select action to perform when external trigger input #0 fires. If external trigger input #0 does not exist, then its action is fixed at 0. 0: No action 1: Reserved 2: Trace-on action When `trTeInstTrigEnable` = 1 it will start instruction tracing (`trTeInstTracing` → 1). When `trTeDataTrigEnable` = 1 it will start data tracing (`trTeDataTracing` → 1). 3: Trace-off action When `trTeInstTrigEnable` = 1 it will stop instruction tracing (`trTeInstTracing` → 0). When `trTeDataTrigEnable` = 1 it will stop data tracing (`trTeDataTracing` → 0). 4: Trace-notify action If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packet with the current PC and, if enabled, a timestamp. 5-15: Reserved	WARL	Undef
31:4	trTeTrigExtInActionN	Select actions (as defined for bits 3-0) for external trigger input #N (1..7). If an external trigger input does not exist, then its action is fixed at 0.	WARL	Undef

Table 13. **Register: trTeTrigExtOutControl: External Trigger Output Control Register (trBaseEncoder+0x058)**
Bit	Field	Description	RW	Reset
3:0	trTeTrigExtOutEvent0	Bitmap to select which event(s) cause external trigger #0 output to fire. If external trigger output #0 does not exist, then all bits are fixed at 0. Bits 2 and 3 may be fixed at 0 if the corresponding feature is not implemented. Bit 0: Start trace transition (`trTeInstTracing` 0 → 1) will fire the trigger. Bit 1: Stop trace transition (`trTeInstTracing` 1 → 0) will fire the trigger. Bit 2-3: Vendor-specific event (optional)	WARL	Undef
31:4	trTeTrigExtOutEventN	Select events for external trigger output #N (1..7). If an external trigger output does not exist, then its event bits are fixed at 0	WARL	Undef

Triggers Precedence

It is implementation dependent what happens when triggers (from debug module or external) with conflicting actions occur simultaneously (signaled at the same ingress port cycle) or if triggers occur too frequently. It is recommended that tracing starts from the oldest instruction retired in the cycle that Trace-on is asserted, and stops following the newest instruction retired in the cycle that Trace-off is asserted.

Trace Encoder Filter Registers

All registers with offsets 0x400 .. 0x7FC are designated for additional trace encoder filter options (context, addresses, modes, etc.).

Trace encoder filters are an optional feature that can be used to control the generated trace in various ways.

The registers below divide the filter logic into filters and comparators to provide maximum flexibility at low cost. The number of filters and comparators depends on the system. Each filter unit can specify filtering against instruction and optionally against data trace inputs from the hart. When filter i is implemented, the registers trTeFilteriControl and trTeInstFilters must be implemented to enable it. And to apply filter i to the data trace, the trTeDataFilters register must also be present. And if a match bit in the trTeFilteriControl register can be set to 1 (= enabling a filter option), the corresponding register from the bit’s description must have a correct value already set as otherwise the trigger may fire unintentionally. Each of the mentioned comparator units is a pair of comparators (primary and secondary, or P and S), so a limited range can be matched with a single comparator unit if needed. Each enabled filter define independent condition where trace is enabled - if several filters are enabled they act as logical OR. Several conditions for single filter act as logical AND.

Filter and comparator registers refer to values of some signals (as priv, itype, ecause, dtype, dsize, …) available on Trace Ingress Port. See E-Trace specification for details of encoding of these values.

Table 14. **Register: trTeFilter??: Trace Encoder Filter Registers (trBaseEncoder+0x400..0x5FF)**
Address Offset	Register Name	Compliance	Description
0x400 + 0x20*i	trTeFilteriControl	Optional	Filter i control
0x404 + 0x20*i	trTeFilteriMatchInst	Optional	Filter i instruction match control
0x408 + 0x20*i	trTeFilteriMatchEcauseLow	Optional	Filter i Ecause match control (bits 31:0)
0x40C + 0x20*i	trTeFilteriMatchEcauseHigh	Optional	Filter i Ecause match control (bits 63:32)
0x410 + 0x20*i	trTeFilteriMatchValueImpdef	Optional	Filter i impdef value
0x414 + 0x20*i	trTeFilteriMatchMaskImpdef	Optional	Filter i impdef mask
0x418 + 0x20*i	trTeFilteriMatchData	Optional	Filter i Data trace match control
0x41C + 0x20*i	—	Optional	Reserved

Table 15. **Register: trTeComp??: Trace Encoder Comparator Registers (trBaseEncoder+0x600..0x6FF)**
Address Offset	Register Name	Compliance	Description
0x600 + 0x20*j	trTeCompjControl	Optional	Comparator j control
0x604 + 0x20*j	—	Optional	Reserved
0x608 + 0x20*j	—	Optional	Reserved
0x60c + 0x20*j	—	Optional	Reserved
0x610 + 0x20*j	trTeCompjPmatchLow	Optional	Comparator j primary match (bits 31:0)
0x614 + 0x20*j	trTeCompjPmatchHigh	Optional	Comparator j primary match (bits 63:32)
0x618 + 0x20*j	trTeCompjSmatchLow	Optional	Comparator j secondary match (bits 31:0)
0x61C + 0x20*j	trTeCompjSmatchHigh	Optional	Comparator j secondary match (bits 63:32)

Table 16. **Register: trTeFilteriControl : Filter i Control Register (trBaseEncoder+0x400 + 0x20i)**
Bit	Field	Description	RW	Reset
0	trTeFilterEnable	Overall filter enable for filter #i	WARL	Undef
1	trTeFilterMatchPrivilege	When set, match privilege levels specified by `trTeFilterMatchChoicePrivilege` field for filter #i.	WARL	Undef
2	trTeFilterMatchEcause	When set, start matching from exception cause codes specified by `trTeFilterMatchChoiceEcause` field for filter #i, and stop matching upon return from the 1st matching exception.	WARL	Undef
3	trTeFilterMatchInterrupt	When set, start matching from either an interrupt or exception as specified by `trTeFilterMatchValueInterrupt` field for filter #i, and stop matching upon return from the 1st matching trap.	WARL	Undef
4	trTeFilterMatchComp1	When set, the output of the comparator selected by `trTeFilterComp1` must be true for the filter to match.	WARL	Undef
7:5	trTeFilterComp1	Specifies the comparator unit to use for the 1st comparison.	WARL	Undef
8	trTeFilterMatchComp2	When set, the output of the comparator selected by `trTeFilterComp2` must be true for the filter to match.	WARL	Undef
11:9	trTeFilterComp2	Specifies the comparator unit to use for the 2nd comparison.	WARL	Undef
12	trTeFilterMatchComp3	When set, the output of the comparator selected by `trTeFilterComp3` must be true for the filter to match.	WARL	Undef
15:13	trTeFilterComp3	Specifies the comparator unit to use for the 3rd comparison.	WARL	Undef
16	trTeFilterMatchImpdef	When set, match impdef values as specified by `trTeFilterMatchValueImpdef` and `trTeFilterMatchMaskImpdef` fields for filter #i.	WARL	Undef
23:17	—	Reserved	—	0
24	trTeFilterMatchDtype	When set, match dtype values as specified by `trTeFilterMatchChoiceDtype` field for filter #i.	WARL	Undef
25	trTeFilterMatchDsize	When set, match dsize values as specified by `trTeFilterMatchChoiceDsize` field for filter #i.	WARL	Undef
31:26	—	Reserved	—	0

Handling of trTeFilterMatchEcause and trTeFilterMatchInterrupt should include a count of nested traps. The size of the counter is implementation dependent. If the number of nested traps exceeds the number that can be counted, the counter will saturate, meaning that the filtering will turn off prematurely.

Table 17. **Register: trTeFilteriMatchInst : Filter i Instruction Match Control Register (trBaseEncoder+0x404 + 0x20i)**
Bit	Field	Description	RW	Reset
7:0	trTeFilterMatchChoicePrivilege	When `trTeFilterMatchPrivilege` field for filter #i is set, match all privilege levels for which the corresponding bit is set. For example, if bit N is 1, then match if the priv value at ingress port is N. Setting several bits allow matching several privileges.	WARL	Undef
8	trTeFilterMatchValueInterrupt	When `trTeFilterMatchInterrupt` field for filter #i is set, match itype of 2 or 1 depending on whether this bit is 1 or 0 respectively.	WARL	Undef
31:9	—	Reserved	—	0

Table 18. **Register: trTeFilteriMatchEcauseLow : Filter i Ecause Match Control (low) Register (trBaseEncoder+0x408 + 0x20i)**
Bit	Field	Description	RW	Reset
31:0	trTeFilterMatchChoiceEcauseLow	When `trTeFilterMatchEcause` field for filter #i is set, match all excepion causes for which the corresponding bit is set. If bit N is 1, then match if the ecause is N.	WARL	Undef

Table 19. **Register: trTeFilteriMatchEcauseHigh : Filter i Ecause Match Control (high) Register (trBaseEncoder+0x40C + 0x20i)**
Bit	Field	Description	RW	Reset
31:0	trTeFilterMatchChoiceEcauseHigh	Stores bits 63:32 to allow matching of higher ecause codes. If bit N is 1, then match if the ecause is N+32.	WARL	Undef

Table 20. **Register: trTeFilteriMatchValueImpdef : Filter i Impdef Match Value Register (trBaseEncoder+0x410 + 0x20i)**
Bit	Field	Description	RW	Reset
31:0	trTeFilterMatchValueImpdef	When `trTeFilterMatchimpdef` field for filter #i is set, match if (impdef & `trTeFilterMatchMaskImpdef`) == (`trTeFilterMatchValueImpdef` & `trTeFilterMatchMaskImpdef`).	WARL	Undef

Table 21. **Register: trTeFilteriMatchMaskImpdef : Filter i Impdef Match Mask Register (trBaseEncoder+0x414 + 0x20i)**
Bit	Field	Description	RW	Reset
31:0	trTeFilterMatchMaskImpdef	When `trTeFilterMatchimpdef` field for filter #i is set, match if (impdef & `trTeFilterMatchMaskImpdef`) == (`trTeFilterMatchValueImpdef` & `trTeFilterMatchMaskImpdef`).	WARL	Undef

Table 22. **Register: trTeFilteriMatchData : Filter i Data Match Control Register (trBaseEncoder+0x418 + 0x20i)**
Bit	Field	Description	RW	Reset
15:0	trTeFilterMatchChoiceDtype	When `trTeFilterMatchDtype` field for filter #i is set, match all data access types for which the corresponding bit is set. For example, if bit N is 1, then match if the dtype value is N.	WARL	Undef
23:16	trTeFilterMatchChoiceDsize	When `trTeFilterMatchDsize` field for filter #i is set, match all data access sizes for which the corresponding bit is set. For example, if bit N is 1, then match if the dsize value is N.	WARL	Undef
31:24	—	Reserved	—	0

Table 23. **Register: trTeCompjControl : Comparator j Control Register (trBaseEncoder+0x600 + 0x20j)**
Bit	Field	Description	RW	Reset
1:0	trTeCompPInput	Determines which input to compare against the primary comparator. 0: iaddr 1: context 2: tval 3: daddr	WARL	Undef
3:2	trTeCompSInput	Determines which input to compare against the secondary comparator. Same encoding as `trTeCompPInput`.	WARL	Undef
6:4	trTeCompPFunction	Selects the primary comparator function. Primary result is true if input selected via `trTeCompPInput` is: 0: equal to `trTeCompPMatch` 1: not equal to `trTeCompPMatch` 2: less than `trTeCompPMatch` 3: less than or equal to `trTeCompPMatch` 4: greater than `trTeCompPMatch` 5: greater than or equal to `trTeCompPMatch` 6: Result always false (input ignored). Prime latch to 1 if `trTeCompMatchMode` is 3 7: Result always true (input ignored)	WARL	Undef
7	—	Reserved	—	0
10:8	trTeCompSFunction	Selects the secondary comparator function. Secondary result is true if input selected via `trTeCompSInput` is: 0: equal to `trTeCompSMatch` 1: not equal to `trTeCompSMatch` 2: less than `trTeCompSMatch` 3: less than or equal to `trTeCompSMatch` 4: greater than `trTeCompSMatch` 5: greater than or equal to `trTeCompSMatch` 6: Result always true (input ignored). Use `trTeCompSMatch` as a mask for `trTeCompPMatch` 7: Result always true (input ignored)	WARL	Undef
11	—	Reserved	—	0
13:12	trTeCompMatchMode	Selects the match condition used to assert the overall comparator output 0: primary result true 1: primary and secondary result both true: (P && S) 2: Either primary or secondary result does not match: !(P && S) 3: Set when primary result is true and continue to assert until instruction after secondary result is true	WARL	Undef
14	trTeCompPNotify	Generate a trace packet explicitly reporting the address of the final instruction in a block that causes a primary match. This is also known as a watchpoint. Requires `trTeCompPInput` to be 0, and has no effect otherwise.	WARL	Undef
15	trTeCompSNotify	Generate a trace packet explicitly reporting the address of the final instruction in a block that causes a secondary match. This is also known as a watchpoint. Requires `trTeCompSInput` to be 0, and has no effect otherwise.	WARL	Undef
31:16	—	Reserved	—	0

Comparisions are performed as unsigned numbers. Only bits from an input signal (as defined by trTeCompPInput and/or trTeCompSInput fields), should be compared. Additional most significant bits from the trTeCompjPMatchLow/High registers must be ignored.

Table 24. **Register: trTeCompjPMatchLow : Comparator j Primary match (low) Register (trBaseEncoder+0x610 + 0x20j)**
Bit	Field	Description	RW	Reset
31:0	trTeCompPMatchLow	The match value for the primary comparator (bits 31:0).	WARL	Undef

Table 25. **Register: trTeCompjPMatchHigh : Comparator j Primary match (high) Register (trBaseEncoder+0x614 + 0x20j)**
Bit	Field	Description	RW	Reset
31:0	trTeCompPMatchHigh	The match value for the primary comparator (bits 63:32).	WARL	Undef

Table 26. **Register: trTeCompjSMatchLow : Comparator j Secondary match (low) Register (trBaseEncoder+0x618 + 0x20j)**
Bit	Field	Description	RW	Reset
31:0	trTeCompSMatchLow	The match value for the secondary comparator (bits 31:0).	WARL	Undef

Table 27. **Register: trTeCompjSMatchHigh : Comparator j Secondary match (high) Register (trBaseEncoder+0x61C + 0x20j)**
Bit	Field	Description	RW	Reset
31:0	trTeCompSMatchHigh	The match value for the secondary comparator (bits 63:32).	WARL	Undef