3.1. Bibliography
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[2] Compute Express® Link (CXL) Specification Revision 3.0, . [Online]. Available: https://www.computeexpresslink.org/download-the-specification
[3] A. Algirdas and L. Jean-Claude and R. B. a. . . . . . . . . . . . L. Carl, "Basic Concepts and Taxonomy of Dependable and Secure Computing", IEEE Trans. Dependable Secur. Comput., vol. 1, no. 1, jan 2004. pp. 11–33, [Online]. Available: https://doi.org/10.1109/TDSC.2004.2.
[4] S. Marc et al., "Addressing Failures in Exascale Computing", Int. J. High Perform. Comput. Appl., vol. 28, no. 2, may 2014. pp. 129–173, [Online]. Available: https://doi.org/10.1177/1094342014522573.
[5] K. Yoongu et al., "Flipping Bits in Memory without Accessing Them: An Experimental Study of DRAM Disturbance Errors" in Proceeding of the 41st Annual International Symposium on Computer Architecuture. IEEE Press, 2014, pp. 361–372.
[6] Radojkovic and Petar, "Towards Resilient EU HPC Systems: A Blueprint" in Proceedings of the 16th ACM International Conference on Computing Frontiers. New York, NY, USA:, Association for Computing Machinery, 2019, pp. 339, Available: https://doi.org/10.1145/3310273.3323434.
[7] C. Franck and A. Geist and G. William and K. Sanjay and K. Bill and S. Marc, "Toward Exascale Resilience: 2014 Update", Supercomput. Front. Innov.: Int. J., vol. 1, no. 1, apr 2014. pp. 5–28, [Online]. Available: https://doi.org/10.14529/jsfi140101.
[8] S. Bianca and P. Eduardo and W. Wolf-Dietrich, "DRAM Errors in the Wild: A Large-Scale Field Study", Commun. ACM, vol. 54, no. 2, feb 2011. pp. 100–107, [Online]. Available: https://doi.org/10.1145/1897816.1897844.
[9] S. Vilas and L. Dean, "A Study of DRAM Failures in the Field" in International Conference on High Performance Computing, Networking, Storage and Analysis (SC). 2012, pp. 76:1—76:11.
[10] Z. Darko et al., "DRAM Errors in the Field: A Statistical Approach" in International Symposium on Memory Systems (MEMSYS). 2019.
[11] H. A. A. and S. I. A. and S. Bianca, "Cosmic Rays Don’t Strike Twice: Understanding the Nature of DRAM Errors and the Implications for System Design" in International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2012.
[12] M. Justin and W. Qiang and K. Sanjeev and M. Onur, "Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field" in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). 2015, pp. 415—426.
[13] T. Dong and C. Peter and T. Zuheir and S. M. W., "Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults" in International Conference on Dependable Systems and Networks (DSN). 2006.
[14] D. Xiaoming et al., "Fault-Aware Prediction-Guided Page Offlining for Uncorrectable Memory Error Prevention" in International Conference on Computer Design (ICCD). 2021.
[15] M. C. Di and K. Zbigniew and I. R. K. and B. Fabio and F. Joseph and K. William, "Lessons Learned from the Analysis of System Failures at Petascale: The Case of Blue Waters" in International Conference on Dependable Systems and Networks (DSN). 2014, pp. 610—621.
[16] D. Xiaoming and L. Cong and Z. Shen and Y. Mao and L. Jing, "Predicting Uncorrectable Memory Errors for Proactive Replacement: An Empirical Study on Large-Scale Field Data" in European Dependable Computing Conference (EDCC). 2020.
[17] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, . [Online]. Available: https://github.com/riscv/riscv-isa-manual
[18] RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, . [Online]. Available: https://github.com/riscv/riscv-isa-manual