Untitled :: RISC-V Ratified Specifications Library

2.1. The ACPI RQSC Table

The Capacity and Bandwidth QoS controllers in a system are described by the ACPI RQSC table. The actual register interface is specified in the RISC-V Capacity and Bandwidth Controller QoS Register Interface specification [2].

The RQSC table describes the properties of the QoS controllers in the system and the resources managed by the each of the QoS controllers. The RQSC table does not describe any topological arrangement of QoS controllers but such topological arrangement may be inferred, when applicable, by determining the topological arrangement of the resources managed by the QoS controller using the ACPI tables that describe the property of those resources.

The capacity or bandwidth controller behavior for handling a request with a non-zero RCID value before configuring the capacity or bandwidth controller respectively with capacity or bandwidth allocation for that RCID is UNSPECIFIED. Software must ensure that the QoS controllers accessed by a request with non-zero RCID values are configured appropriately prior to initiating such requests.

The following diagram illustrates the various components of the RQSC table. The RQSC table contains among other typical ACPI table fields, the count and the list of QoS Controller Structures. Each QoS Controller Structure describes the properties of a QoS Controller and contains one or more Resource Structures. Usually, a QoS controller is associated with a single Resource structure. However, in some implementations, a QoS controller may be associated with multiple Resource structures. Each Resource Structure provides an ACPI locator for the resource governed by that QoS controller.

Figure 1. RQSC Table Components

The RQSC table presents controllers as a flat set and does not directly encode hierarchy. Any hierarchy present in the implementation is conveyed through the association of controllers with resources described elsewhere. For example, if an SoC implements Cache Capacity controllers for both an L2 cache within a core or cluster of cores and a last-level cache (LLC), the hierarchy is captured by the resource associations of those controllers, as indicated by the Cache ID fields in the corresponding PPTT descriptions.

The structure of the RQSC is described in Table 1.

Table 1. The RQSC Table
Field	Byte Length	Byte Offset	Description
Header
- Signature	4	0	'RQSC'. RISC-V Quality of Service Controllers Table.
- Length	4	4	Length of the entire RQSC table in bytes.
- Revision	1	8	Revision number. Current Value: 1
- Checksum	1	9	Entire table must sum to zero
- OEMID	6	10	OEM ID
- OEM Table ID	8	16	For RQSC Table, the table ID is the manufacturer model ID
- OEM Revision	4	24	OEM revision of RQSC Table for supplied OEM Table ID
- Creator ID	4	28	Vendor ID of utility that created the table
- Creator Revision	4	32	Revision of utility that created the table
Body
- Number of QoS Controllers	4	36	The number of system level QoS controller structures that immediately follow.
- QoS Controller Structure [n]	-	40	List of Quality of Service Controller Structures. See Table 2 table below.

Table 2. Quality of Service Controller Structure
Field	Byte Length	Byte Offset	Description
Header
- Controller Type	1	0	Identifies the register interface supported by this controller, as defined by the RISC-V CBQRI Specification. 0 - Capacity 1 - Bandwidth 2-0x7F - Reserved for future standard use 0x80-0xFF - Designated for Vendor specific use
- Reserved	1	1	Reserved. Must be 0
- Length	2	2	Length of the Quality of Service Controller structure in bytes. The Length includes all resource structures for this controller.
- Register Interface Address	12	4	Contains the processor-relative base address, represented in Generic Address Structure (GAS) format, of the controller’s register space.
- RCID Count	2	16	A non-zero value indicates that the controller supports allocation capability and specifies the number of Resource Control IDs (RCIDs) supported by the controller. A value of zero indicates that no allocation control is available. OSPM must use the RCID Count field to determine the number of RCIDs supported by the controller, regardless of any count reported by the hardware.
- MCID Count	2	18	A non-zero value indicates that the controller supports monitoring capability and specifies the number of Monitoring Control IDs (MCIDs) supported by the controller. A value of zero indicates that no monitoring control is available. OSPM must use the MCID Count field to determine the number of MCIDs supported by the controller, regardless of any count reported by the hardware. At least one of RCID Count or MCID Count must be non-zero.
- Controller Flags	2	20	Controller-Specific flags. Refer to Table 3 for details.
- Number of Resources	2	22	Number of Resource structures associated with this QoS controller.
- Resource Structure [n]	-	24	List of Resource Structures associated with this QoS controller.

Table 3. Controller Flags
Bit	Description
0	When set, indicates the controller supports allocating zero capacity blocks or zero bandwidth blocks to an RCID.
1-7	Reserved for future standard use.
8-15	Designated for Vendor specific use.

Table 4. Resource Structure
Field	Byte Length	Byte Offset	Description
Header
- Resource Type	1	0	0 - Cache 1 - Memory 2 - 0x7F - Reserved for future standard use 0x80 - 0xFF - Designated for Vendor specific use
- Reserved	1	1	Reserved. Must be 0
- Length	2	2	Length of this Resource Structure, in bytes. The length includes the Resource-Specific Data bytes. A value of 20 indicates that no Resource-Specific Data is present.
- Resource Flags	2	4	Resource Type Specific flags. Refer to Table 5 for details.
- Reserved	1	6	Reserved. Must be 0
- Resource ID Type	1	7	Type of the Resource ID described by Resource ID 1 and Resource ID 2 fields. 0 - Processor Cache 1 - Memory Range 2 - Memory-Side Cache 3 - ACPI Device: Used in cases where the resource is described as an ACPI device in a platform specific or vendor specific implementation. 4 - PCI Device: Used in cases where the resource is a PCI device in a platform specific or vendor specific implementation. For example, a network interface card implementing ethernet ports. 5 - 0x7F - Reserved for future standard use 0x80 - 0xFF - Designated for Vendor specific use
- Resource ID 1	8	8	Primary identifier for the resource. The interpretation of this field depends on the Resource ID Type. For example, this may contain a Cache ID, Proximity Domain, or device identifier depending on the resource type. Refer to Table 6 for type-specific details.
- Resource ID 2	4	16	Auxiliary identifier for the resource. Some resource types require additional information beyond Resource ID 1 to uniquely identify the resource. For example, ACPI devices may share the same Hardware ID (_HID) and require a Unique ID (_UID) to distinguish them. Refer to Table 7 for type-specific details. Reserved when not required by the resource type.
- Resource Specific Data	-	20	Depends on the Resource Type Field. Refer to Table 8 for details.

Table 5. Resource Flags
Bit	Description
All Other Resource Types
0-7	Reserved for future standard use.
8-15	Designated for Vendor specific use.

Table 6. Resource ID 1
Field	Byte Length	Byte Offset	Description
Resource ID Type [0 - Processor Cache]
Cache ID	4	0	Unique Cache ID from the PPTT table’s Cache Type Structure (Table 5.159 in ACPI Specification 6.5) that this controller is associated with.
Reserved	4	4	Reserved.
Resource ID Type [1 - Memory Affinity Structure]
Proximity Domain	4	0	Proximity domain from the SRAT table’s Memory Affinity Structure the resource is associated with. If the SRAT table is not implemented, then this value shall be 0 indicating a UMA memory configuration.
Reserved	4	4	Reserved.
Resource ID Type [2 - Memory-Side Cache]
Proximity Domain	4	0	Proximity domain from the SRAT table’s Memory Affinity Structure the resource is associated with. If the SRAT table is not implemented, then this value shall be 0 indicating a UMA memory configuration.
Reserved	4	4	Reserved.
Resource ID Type [3 - ACPI Device]
ACPI Hardware ID	8	0	_HID value of the ACPI Device corresponding to the Resource.
Resource ID Type [4 - PCI Device]
PCIe Routing ID	4	0	The combination of a Segment Number, Bus Number, Device Number, and Function Number that uniquely identifies the PCI Express function or SIOV SDI.
Reserved	4	4	Reserved.
All Unspecified Resource ID Types
Resource ID 1	8	0	Reserved.

Table 7. Resource ID 2
Field	Byte Length	Byte Offset	Description
Resource ID Type [2 - Memory-Side Cache]
Cache Level	4	4	The Cache Level of the Memory Side Cache as identified by bits [7:4] of Cache Attributes structure from the corresponding Memory Side Cache Information Structure from HMAT.
Resource ID Type [3 - ACPI Device]
ACPI Unique ID	4	0	_UID value of the ACPI Device corresponding to the Resource.
All Unspecified Resource ID Types
Resource ID 2	4	0	Reserved.

Table 8. Resource Specific Data

Field

Byte Length

Byte Offset

Description

All Unspecified Resource Types

For resource types specified by this specification, if a resource type is not identified below, then there is no Resource Specific Data defined for that resource type and the Length of the Resource Structure must be set to 20.

Resource Type [1 - Memory]

Bandwidth per Block

Indicates the bandwidth, in bytes per second, represented by each unit of the bandwidth block for this resource. If the value is 0, then the bandwidth per block is not provided.

2.1.1. RISC-V Memory Bandwidth QoS Controllers

2.1.1.1. Bandwidth Per Block Calculation

The Memory Bandwidth QoS controllers provide a generic means to control bandwidth in terms of blocks. The user may be interested in knowing exactly how much bandwidth a block entails, so that they can make informed decisions on how to size the per RCID bandwidth block configuration.

Given memory bandwidth will vary based on the type of memory connected to the system, the speed at which they are configured, the number of channels, interleaving conditions, etc., System BIOS or M-mode FW calculates the amount of Bandwidth pertaining to each controller’s block unit. This is done by calculating the total bandwidth of all memory controllers within a memory region (proximity domain) and then dividing the total bandwidth by the number of bandwidth blocks that the controller governing that resource supports.

2.1.2. Shared Resource Configuration

In many system designs, a single logical resource may be managed by multiple QoS controllers. This occurs when the resource is physically distributed across multiple components, or when redundant controllers provide access to the same underlying resource. When multiple QoS controllers share responsibility for the same resource, they must be configured identically to ensure consistent behavior. Mismatched configurations across controllers managing the same resource can lead to unpredictable QoS enforcement and system behavior.

The resource association information provided in the RQSC table enables software to identify which controllers share responsibility for a common resource and must therefore maintain synchronized configurations.

2.1.2.1. Example: Memory Bandwidth Controllers in UMA and NUMA Configurations

System memory can be configured in one of two modes:

UMA (Uniform Memory Access): All memory channels across different controllers are treated as a single unified memory range. Memory traffic is distributed equally among all controllers through interleaved addressing. In this configuration, memory affinity structures typically either omit memory descriptions entirely or describe all memory regions with the same proximity domain.
NUMA (Non-Uniform Memory Access): Memory controllers are grouped into separate domains, with memory addresses partitioned among different channel groups. Within each NUMA node, traffic is still distributed equally among controllers through interleaved addressing. In this configuration, memory affinity structures describe memory regions with different proximity domains corresponding to their respective NUMA nodes.

In both configurations, when multiple memory bandwidth QoS controllers share the same proximity domain, their bandwidth reservation settings must be configured identically to ensure consistent bandwidth enforcement across all memory channels within that domain.